• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.1
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• pp.28-37
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• 2016

Fault locating is an important element to minimize the damage of power system. The computation error of fault locator may occur by the influence of the DC offset component during phasor extraction. In order to minimize the bad effects of DC offset component, this paper presents an improved fault location algorithm based on a DC offset removal filter for short fault in a double circuit transmission line. We have modeled a 154kV double circuit transmission line by the ATP software to demonstrate the effectiveness of the proposed fault locating algorithm. The line to line short faults were simulated and then collected simulation data was used. It can be seen that the error rate of fault locating estimation by the proposed algorithm decreases than the error rate of fault locating estimation by conventional algorithm.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.371-373
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• 2005

An enhancement for a transmission and substation equipment in power system make the system impedance to be lower. In principle, if the system impedance become low, system stability will be better, but the fault current become very higher. It is a very big problem for CB operating. As a fact of CB operating performance, high amplitude of the fault current may cause CB operation failure because of exceeding standard value in TRV. So we simulated TRV by using the EMTP. Generally there are two types of TRV in actual power system. One is short line fault, the other is bus terminal fault. In this paper, we simulated the TRv at short line fault as installed current limit reactors to reduce fault current in 345kV ultra-high voltage system. Short line fault is caused from single line fault in transmission line.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1783-1785
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• 2001

With the 4-MJ synthetic testing facilities completed, KERI can perform the circuit breaker testing up to 420 kV, 50 kA ratings. The short-line fault test is one of the necessary test items which are required for the circuit breaker, and in order to perform the short-line fault test KERI(Korea Electrotechnology Institute) has used the "new artificial line" which has small dimension and is easy to generate the saw-tooth wave. This paper describes the following items of the new artificial line. -Description of 4-kinds of artificial lines and determination of the circuit parameter of artificial line. -TRV characteristics of saw-tooth waves for each circuit. -KERI's artificial line.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.2
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• pp.148-152
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• 2010

The superconducting fault current limiter (SFCL) applied into the neural line of a power system, which can limit the unsymmetrical fault current from the single-line ground fault or the double-line ground fault, was reported to be the effective application location of the SFCL in a power system. However, the limiting operation for the symmetrical fault current like the triple line-ground fault is not effective because of properties of the balanced three-phase system. In this paper, the limiting method of the symmetrical fault current in a power system with a SFCL applied into neutral line was suggested. Through the short-circuit experiments of the three-phase fault types for the suggested method, the fault current limiting and recovery characteristics of the SFCL in the neutral line were analyzed and the effectiveness of the suggested method was described.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.402-404
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• 2006

In this paper, we simulated transient-state under fault in stator windings of synchronous generator. The fault types are line to ground fault, line to line short fault, and three phase short fault. For fault analysis of generator system, the voltage equation of a synchronous machine using the two-axis theory was used. It can be used to analyze important features of faults and to develop enhanced protection methods.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1818-1823
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• 2015

In this paper, we analyzed the optimal configuration of protection wire that have been installed in the electric railway power supply system. Protection wires are to suppress the ground potential rise when the short circuit fault between contact wire-rail(C-F), and protect the electronics equipments(signalling and communication) that are facility the wayside. The role of protection wires must be feed back quickly the fault current to the substation when a short circuit fault occurs. In this paper, we proposed that only one line to install the protection wire. Comparing how to newly proposed and existing system, most of the performance is similar. The reason is that most of the current flowing in the protection wire near the location where the fault occurred. There is no problem even if in one line for human safe and the low impedance of the return circuit in dimension to ensure the safety of the facility during the fault. To ensure safety during an fault occurs, it is sufficient even by one line. But, In the protection wire of facilities planning it is necessary to design taking into account the potential utility.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.154-156
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• 1993

In this paper, fault analysis using simulation method and fault diagnosis scheme are presented for induction motor drive system. Major faults such as inverter 'a' phase open fault, inverter 'a'-'b' phase short circuit fault and inverter 'a' phase ground fault are analyzed and simulated. On-line and off-line fault diagnosis systems are proposed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.6
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• pp.955-961
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• 2016

Fault location estimation is an important element for rapid recovery of power system when fault occur in transmission line. In order to calculate line impedance, most of fault location algorithm uses by measuring relaying waveform using DFT. So if there is a calculation error due to the influence of phasor by DC offset component, due to large vibration by line impedance computation, abnormal and non-operation of fault locator can be issue. It is very important to implement the robust fault location algorithm that is not affected by DC offset component. This paper describes an enhanced fault location algorithm based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any erstwhile information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced fault location algorithm uses DFT filter as well as the proposed DC offset filter. The behavior of the proposed fault location algorithm using off-line simulation has been verified by data about several fault conditions generated by the ATP simulation program.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.976-978
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• 1998

In this paper, we designed basic concept and structure of bypassing device which promoted the activity of low voltage line-fuse, when it perceived the too small short-fault current to activate line-fuse which located at the between secondary of pole transformer and home immediately. And we study displacement of bypass contact and electromagnetic force caused by the short-fault current by the basic experiment to understand the basic characteristic of bypassing movements.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2139-2146
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• 2008

This paper presents a numerical algorithm for fault location estimation which used to data from both end of the transmission line. The proposed algorithm is also based on the synchronized voltage and current phasor measured from the PMUs(Phasor Measurement Units) in the time-domain. This paper has separated from two part of with/without shunt capacitance(short/long distance). Most fault was arc one-ground fault which is 75% over [1]. so most study focused with it. In this paper, the numerical algorithm has calculated to distance for ground fault and line-line fault. In this paper, the algorithm is given with/without shunt capacitance using II parameter line model, simple impedance model and estimated using DFT(Discrete Fourier Transform) and the LES(Least Error Squares Method). To verify the validity of the proposed algorithm, the EMTP(Electro- Magnetic Transient Program) and MATLAB did used.