• Title/Summary/Keyword: Short channel effect

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The Effects of Price on Consumers' Purchasing Behavior for Eco-Friendly Foods (소비자의 친환경농산물 구매에 있어서 가격변수의 중요도 및 영향인자에 관한 분석)

  • Jin, Hyun-Joung;Keum, Seck-Hun
    • Journal of Distribution Research
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    • v.16 no.3
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    • pp.105-133
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    • 2011
  • Short Abstract: This study investigates the effects of price and other variables on consumers' purchasing decision for eco-friendly foods. This study pays particular attention to the effect of price that may influences consumers' decision to buy eco-friendly foods. The empirical findings are summarized as follows. First, the descriptive results of the survey show that "detailed explanation for the products," "distribution channel," "reliability of the labeling for eco-friendly foods" are more important than price and other factors. Second, the ordered logit analysis vindicates that such situational factors as number of children and existence of patient in the family are the most important variables to explain the degree of satisfaction level when considering the price level of eco-friendly foods. Finally, the results of the conjoint analysis indicate that consumers regard distribution channel as the most important factor, and reliability of labeling system and level of price position second and third, respectively. The present study concludes with suggesting some policy implications and directing future studies.

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Performance Analysis of RS, Turbo and LDPC Code in the Binary Symmetric Erasure Channel (이진 대칭 소실 채널에서 RS, 터보 및 저밀도 패리티 검사 부호의 성능 분석)

  • Lim, Hyung-Taek;Park, Myung-Jong;Kang, Seog-Geun;Joo, Eon-Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2C
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    • pp.219-228
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    • 2010
  • In this paper, performance of RS (Reed-Solomon), turbo and LDPC (low density parity check) code in the binary symmetric erasure channel is investigated. When the average erasure length is reduced, the frequency of short erasures is increased. The RS code shows serious performance degradation in such an environment since decoding is carried out symbol-by-symbol. As the erasure length is increased, however, the RS code shows much improved en-or performance. On the other hand, the message and corresponding parity symbols of the turbo code can be erased at the same time for the long erasures. Accordingly, iterative decoding of the turbo code can not improve error performance any more for such a long erasure. The LDPC code shows little difference in error performance with respect to the variation of the average erasure length due to the virtual interleaving effect. As a result, the LDPC code has much better erasure decoding performance than the RS and turbo code.

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

  • Kim, Kwan-Young;Jang, Jae-Man;Yun, Dae-Youn;Kim, Dong-Myong;Kim, Dae-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.134-142
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    • 2010
  • A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

Two-dimensional measurements of the ELM filament using a multi-channel electrical probe array with high time resolution at the far SOL region in the KSTAR

  • Hong, Young-Hun;Kim, Kwan-Yong;Kim, Ju-Ho;Son, Soo-Hyun;Lee, Hyung-Ho;Eo, Hyun-Dong;Kim, Min-Seok;Hong, Suk-Ho;Chung, Chin-Wook
    • Nuclear Engineering and Technology
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    • v.54 no.10
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    • pp.3717-3723
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    • 2022
  • For the first time, two-dimensional temporal behavior of the edge localized mode (ELM) filament is measured in the edge tokamak plasma with a multi-channel electrical probe array (MCEP). MCEP, which has 16 floating probes (4 × 4), is mounted at the far scrape-off layer (SOL) region in the KSTAR. An electron temperature and an ion flux are measured by sideband method (SBM), which can achieve two-dimensional measurements with high time resolution. Furthermore, temporal evolutions of the electron temperature and the ion flux are obtained during the ELM occurrence. In the H-mode period, short spikes from ELM bursts are observed in measured plasma parameters, and the trend is similar to that of typical Hα signal. Interestingly, when blob-like ELM filaments crash the probe, the heat flux is significantly higher in a local region of the probe array. The results show that our probe array using the SBM can measure the ELM behavior and the plasma parameters without the effect of the stray current caused by the huge device. This study can provide valuable data needed to understand the interaction between the SOL plasma and the plasma facing components (PFCs).

A Study on Numerical Analysis for Debris Flow considering the Application of Debris Flow Mitigation Facilities (토석류 저감시설 적용에 따른 토석류 수치해석에 관한 연구)

  • Bae Dong Kang;Jung Soo An;Kye Won Jun;Chang Deok Jang
    • Journal of Korean Society of Disaster and Security
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    • v.16 no.4
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    • pp.33-43
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    • 2023
  • The impact of prolonged rainfall, such as during the monsoon season or intense concentrated rainfall over a short period, can lead to mountainous disasters such as landslides and debris flows. These events, such as landslides and debris flows, cause both human and material damage, prompting the implementation of various measures and research to prevent them. In the context of researching debris flow disasters, numerical models for debris flows provide a relatively simple way to analyze the risk in a study area. However, since empirical equations are applied in these models, yielding different results and variations in input variables across models, the validation of numerical models becomes essential. In this study, a numerical model for debris flows was employed to compare and analyze the mitigation effects of facilities such as check dams and water channel work, aiming to reduce the damage caused by debris flows.

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

  • Cho, Seong-Jae;Sun, Min-Chul;Kim, Ga-Ram;Kamins, Theodore I.;Park, Byung-Gook;Harris, James S. Jr.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.3
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    • pp.182-189
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    • 2011
  • In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

Fabrication, Mesurement and Evaluation of Silicon-Gate n-well CMOS Devices (실리콘 게이트 n-well CMOS 소자의 제작, 측정 및 평가)

  • Ryu, Jong-Seon;Kim, Gwang-Su;Kim, Bo-U
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.5
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    • pp.46-54
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    • 1984
  • A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

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A Causality Analysis of the Prices between Imported Fisheries and Domestic Fisheries in Distribution Channel (수입 수산물과 국내산 수산물의 가격간 유통단계별 인과성 분석 : 명태, 갈치, 조기 냉동품을 대상으로)

  • Cha, Young-Gi;Kim, Ki-Soo
    • The Journal of Fisheries Business Administration
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    • v.40 no.2
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    • pp.105-126
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    • 2009
  • This study applies the cointegration theory to analyse the causality of the prices between imported fisheries and domestic fisheries in distribution channel. We've focused on the prices of import, wholesale and retail about the frozen Alaska pollack, hairtail and croaker which take up high portion and are popular among most of the consumers. In process of analysis, the unit root test was adopted to find the stability of time series data prior to the cointegration test. If the time series data was found as stable one in unit root test, we should analyse the VAR model. If unstable, the cointegratioin test was adopeted to find the long-run equilibrium relationship between the data. When the long-run equilibrium relationship was found among the price of the import, wholesale and retail price, the VECM model was adoped. If not, the differenced VAR model was adopted. The main findings of this study could be summarized as follows ; First, according to the result of the analysis on VAR model, time series data of frozen Alaska pollack was found as stable and has causality relationship and close effect was existing among the import, wholesale and retail price. Second, the data of frozen hairtail was found as an unstable one in unit root test and the result of cointegration test showed the long-run equilibrium relationship at lag 1. From the results of VECM model, we could find that the coefficient of error correction is effective, and the sign is negative(-). It means that the existence of adjustment tendency to long-run equilibrium after a short-run deviation. But the short-run causality of the prices were not found except the price of wholesale. Third, according to the results of differenced VAR model, data from frozen croaker did not have the stability and long-run equilibrium. Moreover, it was found that the import price has a weak causality on the retail price. Because of having difficulties in collecting data, the result of this paper could not explain the relationship among the prices of import, wholesale and retail perfectly. However, it more or less contributed to a long-lasted debate on the direction of causality of price-setting in academic research and provided a useful guide for the policy makers in charge of the price-setting of fisheries products as well.

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A Study on the Propulsion Performance of KCS in Still Water and Regular Wave

  • Lee, Sang-Min;Jeong, Uh-Cheul;Kim, Dae-Hae
    • Journal of Navigation and Port Research
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    • v.37 no.1
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    • pp.63-69
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    • 2013
  • Since most merchant vessels are mainly influenced by the added resistance in an actual sea, they could be navigated more efficiently if this added resistance could be precisely predicted and then effectively reduced. In this paper, we have computed the effective horsepower based on the resistance performance in still water and then calculated the added resistance in regular wave in order to estimate a ship's propulsion performance on a voyage. Firstly, we have performed experiments using a model of KCS in a circulating water channel to estimate the flow characteristics around a container ship and the ship's resistance in still water. Then we have calculated the motion response function in regular wave as well as the values for the increase in resistance, and evaluated the ship's motion performance in waves according to the calculated response function. It was found that the resistance in waves increased because the ship's motion response value became larger as the ship's speed increased in the case of head sea. The effect of the added resistance could be reduced by maneuvering the ship to the encounter angle of $120^{\circ}$ in areas of long wavelengths and to head sea in areas of short wavelengths.

Fin의 두께와 높이 변화에 따른 22 nm FinFET Flash Memory에서의 전기적 특성

  • Seo, Seong-Eun;Kim, Tae-Hwan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.329-329
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    • 2012
  • Mobile 기기로 둘러싸여있는 현대의 환경에서 Flash memory에 대한 중요성은 날로 더해가고 있다. Flash memory의 가격 경쟁력 강화와 사용되는 기기의 소형화를 위해 flash memory의 비례축소가 중요한 문제로 부각되고 있다. 그러나 다결정 실리콘을 플로팅 게이트로 이용하는planar flash memory 소자의 경우 비례 축소 시 short channel effect 와 leakage current, subthreshold swing의 증가로 인한 성능저하와 같은 문제들로 인해 한계에 다다르고 있다. 이를 해결하기 위해 CTF 메모리 소자, nanowire FET, FinFET과 같은 새로운 구조를 가지는 메모리소자에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 22 nm 게이트 크기의 FinFET 구조를 가지는 플래시 메모리소자에서 fin의 두께와 높이의 변화에 따른 메모리 소자의 전기적 특성을 3-dimensional 구조에서 technology computer aided design ( TCAD ) tool을 이용하여 시뮬레이션 하였다. 본 연구에서는 3D FinFET 구조를 가진 플래시 메모리에 대한 시뮬레이션 하였다. FinFET 구조에서 채널영역은 planar 구조와 다르게 표면층이 multi-orientation을 가지므로 본 계산에서는 multi-orientation Lombardi mobility model을 이용하여 계산하였다. 계산에 사용된 FinFET flash memory 구조는 substrate의 도핑농도는 $1{\times}10^{18}$로 하였으며 source, drain, gate의 도핑농도는 $1{\times}10^{20}$으로 설정하여 계산하였다. Fin 높이는 28 nm로 고정한 상태에서 fin의 두께는 12 nm부터 28nm까지 6단계로 나누어서 각 구조에 대한 프로그램 특성과 전기적 특성을 관찰 하였다. 계산결과 FinFET 구조의 fin 두께가 두꺼워 질수록 채널형성이 늦어져 threshold voltage 값이 커지게 되고 subthreshold swing 값 또한 증가하여 전기적 특성이 나빠짐을 확인하였다. 각 구조에서의 전기장과 전기적 위치에너지의 분포가 fin의 두께에 따라 달라지므로써 이로 인해 프로그램 특성과 전기적 특성이 변화함을 확인하였다.

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