• Title/Summary/Keyword: Short channel

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Short Channel n-MOSFET의 Breakdown 전압

  • Kim, Gwang-Su;Lee, Jin-Hyo
    • ETRI Journal
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    • v.9 no.1
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    • pp.118-124
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    • 1987
  • Short channel n-MOSFET의 드레인-소오스 사이의 breakdown은 단순한 접합 breakdown이 아닌 avalanche-induced breakdown으로 p-MOSFET, long channel n-MOSFET의 breakdown 전압보다 훨씬 작은 값을 갖는다. Short channel n-MOSFET의 breakdown의 특징은 current-controlled 부저항 특성(snapback)이 나타나고, 게이트 전압에 따라 breakdown 전압보다 작은 sustainning 전압이 존재한다. 이와 같은 sustainning 전압은 short channel n-MOSFET의 안정한 동작에 또 하나의 제한 요소가 될 수 있다. 따라서 공정 및 회로 시뮬레이션을 위해, short channel n-MOSFET의 avalanche breakdown 현상에 대한 정확한 분석이 요구된다. Short channel n -MOSFET의 avalanche breakdown 현상을 분석하기 위해서Parasitic bipolar transistor를 도입한 분석적 모델을 이용하였다.

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A study of electrical stress on short channel poly-Si thin film transistors (짧은 채널 길이의 다결정 실리콘 박막 트랜지스터의 전기적 스트레스에 대한 연구)

  • 최권영;김용상;한민구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.8
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    • pp.126-132
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    • 1995
  • The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

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A study on the threshold Voltage Model for Short-channel EIGFET (Short-Channel EIGFET의 Threshold 전압 모델에 관한 연구)

  • Park, Gwang-Min;Kim, Hong-Bae;Gwak, Gye-Dal
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.4
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    • pp.1-7
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    • 1985
  • In this paper, a more improved threshold voltage model dependent on drain voltage and substrate bias for short - channel enhancement - mode IGFET is presented. Especially, compared with the several recently published models, the error is sufficiently reduced with the precise analysis on the correction factor for short-channel effect and the calculated values using this model are also agreed well with the experimental data about 1$\mu$m - channel length device.

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A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

  • Yu, Sang Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.3
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    • pp.213-223
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    • 2013
  • A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

Analytical modeling for the short-channel MOSFET (Short-Channel MOSFET의 해석적 모델링)

  • 홍순석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.11
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    • pp.1290-1298
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    • 1992
  • In this paper, the Poisson's equation is solved two-dimensionally without employing any fitting parameters, and the model formulation of a short-channel MOSFET is accomplished fully analytically. It automatically derives a very accurate drain current expression that can be used simultaneously for strong inversion, subthreshold, and saturation regions. Furthermore, this model gives a unified explanation for the short-channel effect, the body effect, the DIBL effect, and even the variation of the effective carrier mobility. The obtained expression of the threshold voltage also includes the dependence on the oxide thickness, the n+ junction depth, and temperature.

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The Characterizing Analysis of a Buried-Channel MOSFET based on the 3-D Numerical Simulation

  • Kim, Man-Ho;Kim, Jong-Soo
    • Journal of Electrical Engineering and Technology
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    • v.2 no.2
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    • pp.267-273
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    • 2007
  • A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

Control of Short-Channel Effects in Nano DG MOSFET Using Gaussian-Channel Doping Profile

  • Charmi, Morteza
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.5
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    • pp.270-274
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    • 2016
  • This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's

  • Omura, Yasuhisa;Konishi, Hideki;Yoshimoto, Kazuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.302-310
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    • 2008
  • This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

3-D Characterizing Analysis of Buried-Channel MOSFETs (매몰공핍형 MOS 트랜지스터의 3차원 특성 분석)

  • Kim, M. H.
    • Proceedings of the Optical Society of Korea Conference
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    • 2000.08a
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    • pp.162-163
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    • 2000
  • We have observed the short-channel effect, narrow-channel effect and small-geometry effect in terms of a variation of the threshold voltage. For a short-channel effect the threshold voltage was largely determined by the DIBL effect which stimulates more carrier injection in the channel by reducing the potential barrier between the source and channel. The effect becomes more significant for a shorter-channel device. However, the potential, field and current density distributions in the channel along the transverse direction showed a better uniformity for shorter-channel devices under the same voltage conditions. The uniformity of the current density distribution near the drain on the potential minimum point becomes worse with increasing the drain voltage due to the enhanced DIBL effect. This means that considerations for channel-width effect should be given due to the variation of the channel distributions for short-channel devices. For CCDs which are always operated at a pinch-off state the channel uniformity thus becomes significant since they often use a device structure with a channel length of > 4 ${\mu}{\textrm}{m}$ and a very high drain (or diffusion) voltage. (omitted)

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Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.170-177
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    • 2008
  • In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.