• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.1
• /
• pp.72-79
• /
• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.55 no.7
• /
• pp.297-305
• /
• 2006

This paper summarizes a development of visualization software for protective engineering in low-voltage power systems. The study is concentrated on the following aspects. First, a software engineering method is applied for designing the object-oriented program. The design and implementation of a Graphic User Interface(GUI) and its integration to a power system framework are developed using object-oriented programming(OOP) in Visual C++. Second, we develop the short circuit analysis module that oriented a low-voltage power system. It is possible to calculate a peak, symmetrical RMS, DC component and asymmetrical fault currents for each time. And it is the first software that can calculate the fault current for single branch of three-phase system. The calculation accuracy is compared with commercial software, and the libraries of low-voltage components are served for convenience use. Third, protective engineering functions are equipped. It is possible to automatically select the circuit breaker which based on the user input characteristics and the fault current calculation and examine the protective coordination. Through the case study, we verified that the developed software can be effectively used to examine the protective engineering in low-voltage power systems.

• Current Optics and Photonics
• /
• v.1 no.1
• /
• pp.7-11
• /
• 2017

In this study, multilayered graphene was easily transferred to the target substrate in one step using thermal release tape. The transmittance of the transferred graphene according to the number of layers was measured using a spectrophotometer. The sheet resistance was measured using a four-point probe system. Graphene formed using this transfer method showed almost the same electrical and optical properties as that formed using the conventional poly (methyl methacrylate) transfer method. This method is suitable for the mass production of graphene because of the short process time and easy large-area transfer. In addition, multilayered graphene can be transferred on various substrates without wetting problem using the one-step dry transfer method. In this work, this easy transfer method was used for dielectric substrates such as glass, paper and polyethylene terephthalate, and a sheet resistance of ~240 ohm/sq was obtained with three-layer graphene. By fabricating organic solar cells, we verified the feasibility of using this method for optoelectronic devices.

• Journal of the Korean Society of Industry Convergence
• /
• v.26 no.6_2
• /
• pp.1117-1125
• /
• 2023

The DC part of the DC microgrid power conversion system uses capacitors for buffers of charge and discharge energy for smoothing voltage and plays important roles such as high frequency component absorption, power balancing, and voltage ripple reduction. The capacitor uses an aluminum electrolytic capacitor, which has advantages of capacity, low price, and relatively fast charging/discharging characteristics. Aluminum electrolytic capacitors(AEC) have previous advantages, but over time, the capacity of the capacitors decreases due to deterioration and an increase in internal temperature, resulting in a decrease in use efficiency or an accident such as steam extraction due to electrolyte evaporation. It is necessary to take measures to prevent accidents because the failure diagnosis and detection of such capacitors are a very important part of the long-term operation, safety of use, and reliability of the power conversion system because the failure of the capacitor leads to not only a single problem but also a short circuit accident of the power conversion system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.322-330
• /
• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.48-55
• /
• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.7
• /
• pp.50-57
• /
• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.1
• /
• pp.153-162
• /
• 2018

The importance of energy harvesting technique is increasing due to the elevated level of demand for sustainable power sources for wearable device applications. In this study, we developed an Energy Harvesting wearable Platform(EH-P) architecture which is used in the design of a multi-energy source based on TENG. The proposed switching circuit produces power with higher current at lower voltage from energy harvesting sources with lower current at higher voltage. This can powers microcontrollers for a short period of time by using PV and TENG complementarily placed under hard conditions for the sources such as indoors. As a result, the whole interface circuit is completely self-powered with this makes it possible to run of sensing on a Wearable device platform. It was possible to increase the wearable device life time by supplying more than 29% of the power consumption to wearable devices. The results presented in this paper show the potential of multi-energy harvesting platform for use in wearable harvesting applications, provide a means of choosing the energy harvesting source.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.10
• /
• pp.17-28
• /
• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2006.11a
• /
• pp.258-261
• /
• 2006

This study introduces the control of duration time of impulse noises emitted from a high voltage COS fuse of a transformer. When a high voltage COS fuse becomes a short circuit by the over current, the peak sound pressure level over 150 dB(A) is generated at the distance of 2m from a COS Fuse. For the purpose of the reduction of impulse noise, in this study, the reactive type silencer has been utilized. And also electrical interrupting test was experimented. From the experimental results, the reactive type silencer has been shown to have the noise reduction of about 13 dB(A). It has been found that the electrical interception performance of the COS fuse was related to the control of the duration time of impulse noise.