• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.889-896
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• 2006

ATM Forum has defined a guaranteed frame rate (GFR) service to serve Internet traffic efficiently. The GFR service provides virtual connections (VCs) for minimum cell rate (MCR) guarantees and allows them to fairly share the residual bandwidth. And ATM Forum has recommended a frame-based generic cell rate algorithm (F-GCRA) as a frame classifier, which determines whether an Am cell is eligible to use the guaranteed bandwidth in a frame level. An ATM switch accommodates cells in its buffer or drops them in a frame level according to current buffer occupancy. A FIFO shared buffer has so simple structure as to be feasibly implemented in switches, but has not been able to provide an MCR guarantee for each VC without buffer management based on per-VC accounting. In this paper, we enhance the F-GCRA frame classifier to guarantee an MCR of each VC without buffer management based on per-VC accounting. The enhanced frame classifier considers burstness of TCP traffic caused by congestion control algorithm so as to enable each VC to use its reserved bandwidth sufficiently. In addition, it is able to alleviate the unfairness problem in usage of the residual bandwidth. Simulation results show that the enhanced frame classifier satisfies quality of services (QoSs) of the GFR service for the TCP traffic.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.79-81
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• 2002

최근에는 ATM, Fast Switched LAN, Fiber Channel과 같은 고속의 네트워크의 발달로 인해 분산 환경의 네트워크 파일 시스템에서 디스크를 접근하는 속도보다 원격지 클라이언트의 메모리를 접근하는 속도가 현저하게 증가되었다. 실제로 이와 같은 고속 네트워크 환경을 기반으로 하여 각 서버와 저장 장치를 분리하여 대용량 데이터를 관리하는 SAN(Storage Area Network)과 같은 새로운 네트워크 저장 시스템이 출연하고 있다. 본 논문에서는 이와 같은 새로운 분산 네트워크 파일 저장 시스템 환경에서 필수적으로 고려되어야 하는 광역 버퍼관리기를 설계 및 구현하였다. 본 논문에서 구현된 광역 버퍼 관리기는 크게 데이터 룩업과 버퍼리스트 관리 부분으로 나누어 구성되어 있으며, 이를 위한 적절한 자죠 구조와 시스템 내에 있는 각 호스트간의 버퍼블록정보 유지를 위한 방안 및 기존 운영체제의 커널내 버퍼 관리기와 통합하는 방안을 제시한다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.4
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• pp.1-11
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• 1999

본 논문에서는 각 유니캐스트 셀이 세 번의 연속된 셀 읽기 싸이클마다 공유 버퍼에서 셀을 읽을 수 있고 멀티캐스트 셀은 마지막 읽기 싸이클에서 유니캐스트 셀을 읽기 위해 공유 버퍼가 사용되지 않을 경우에만 읽히도록 하는 공유 다중버퍼형 ATM 교환기를 제안한다. 유니캐스트 셀에 대한 HOL효과는 멀티캐스트 셀에 의해 영향을 받지 않으며, 유니캐스트 셀 뿐 아니라 멀티캐스트 셀도 각 출력 포트에서 읽힐 수 있는 기회가 생기므로 출력 포트의 이용율이 증가한다. 고정된 멀티캐스트 셀 비율에서, 제안된 방법은 제공부하가 1일 경우에도 98.9%의 수율을 보인다. 제안된 공유 다중 버퍼형 ATM교환기는 0.6㎛ single-poly triple metal CMOS 공정을 사용하여 설계되었다. 설계된 교환기는 8×8의 포트 크기를 가지며 STM-1의 대역폭 155.52Mbps를 각 포트에서 지원할 수 있도록 20MHz에서 동작한다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.1
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• pp.100-108
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• 2003

By choosing Multicast for transmission of educational contents in the Remote Educational System, we can reduce the server load and increase network bandwidth utilization. We design and implement Multicast Middleware for the Remote Educational System in this paper. There are three characteristics in this Multicast Middleware: 1) Through Centralized Multicast Group Management for passive members, it allows a host to make multicast group, which is composed of receivers, called Group Member and who are chosen by the host, called group Maker. Because, all groups are created by the Group Maker in Centralized Group Management, Group Member's join action will be passive 2) Maintenance and recovery of multicast group information in order to restore from exception and crash; the maintenance and recovery mechanism of Group Maker is distinct from that of Group Member. 3) The mechanism which enables to transmit large size multimedia data through multicasting and remove additional copy operation through shared buffer. Fragmentation/de-fragmentation for large data delivery results in additional copy operation in user level. But by using user level shared buffer, it can be done without user Bevel copy operation. By applying to Remote Educational environment which consists of 30 PCs and Fast Ethernet, we can examine the efficiency of this middleware, which can transmit 18frames/sec movie which resolution 320 $\times$ 120 pixels, 128Kbps encoded sound data and some text data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.316-324
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• 2010

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 ${\mu}m$ EEPROM process is $1581.55{\mu}m{\times}792.00{\mu}m$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11B
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• pp.784-791
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• 2005

To provide VoD Service on the Internet VoD server is required to have a large amount of system resource and network bandwidth. Therefore, overlay Multicast schemes are considered as suitable alternatives but they also have some drawbacks to support on-demand media services. In this paper, we propose an overlay multicast based on-demand media service scheme which could exploit server's system resource and its network bandwidth efficiently. Proposed scheme uses shared buffer of clients involving the relay of traffic and Patching while it gives no restrictions to this scheme compared with unicast. Our simulation results show that proposed scheme can support more user than unicast and improve the network performance at the same time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1768-1789
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• 2016

In contemporary video streaming systems based on HTTP protocol, video players at the client side are responsible for adjusting video quality to network conditions and user expectations. However, when multiple video clips are streamed simultaneously, an intricate application logic implemented in the video players overlays the TCP mechanism which is responsible for a balanced access to a shared network link. As a result, some video players may not obtain a fair share of network throughput and may be vulnerable to an unstable video bit-rate. Therefore, we propose to simplify the algorithms implemented in the video players, which are responsible for the adjustment of video quality and constrain their functionality only to sending feedback to a server about a state of the player buffer. The main logic of the system is shifted to the server, which is now responsible for bit-rate selection and prioritisation of the video streams transmitted to multiple clients. To verify our proposition, we performed several experiments in a laboratory environment which show that when the server cooperates with the clients, the video players experience fewer quality switches and the system achieves better fairness when allocating network throughput among the video players. However, this comes at the cost of worse utilisation of network bandwidth.