• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.136-142
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• 2006

Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Journal of Internet Computing and Services
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• v.7 no.6
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• pp.113-121
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• 2006

To reduce switch cost, the optimum numbers of tunable wavelength converters (TWCs) and internal wavelengths required for contention resolution of asynchronous and variable length packets like internet traffics, is presented in the optical packet switch (OPS) with the shared fiber delay line (FDL) buffer. To optimize TWCs and internal wavelength related to on OPS design cost, we proposed a scheduling algorithm for the limited TWCs and internal wavelengths. For three TWC alternatives (not shared, partially shared, and fully shared cases), the optimum numbers of TWCs and internal wavelengths to guarantee minimum pocket loss are evaluated to prevent resource waste. Under o given load, TWCs and internal wavelengths could be significantly reduced, guaranteeing the same pocket loss probability as the performance of on OPS with full TWCs and internal wavelengths.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.899-902
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• 2005

Pipeline hazard due to branch instructions is the major factor of the degradation on the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the branch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a tag memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single shared tag memory, we can expect the smaller ship size and the faster prediction. This hared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.139-151
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• 1997

An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convent IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we concern the cell reassembly mechanism among them, mainly focussed on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as measage loss probability, mean number of message queued in buffer and average reassembly delay are obtianed in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Journal of KIISE:Databases
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• v.30 no.6
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• pp.629-640
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• 2003

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. In the SD cluster, a transaction routing corresponds to select a node for an incoming transaction to be executed. An affinity-based routing can increase local buffer hit ratio of each node by clustering transactions referencing similar data to be executed on the same node. However, the affinity-based routing is very much non-adaptive to the changes in the system load, and thus a specific node will be overloaded if transactions in some class are congested. In this paper, we propose a dynamic transaction routing scheme that can achieve an optimal balance between affinity-based routing and dynamic load balancing of all the nodes in the SD cluster. The proposed scheme is novel in the sense that it can improve the system performance by increasing the local buffer hit ratio and reducing the buffer invalidation overhead.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

• Journal of the Korea Society for Simulation
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• v.28 no.3
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• pp.65-74
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• 2019

For many years, it has been widely studied on fork-join production systems but there is not much literature focusing on the finite buffer(s) of either individuals or shared, and generally distributed processing times. Usually, it is difficult to handle finite buffer(s) through a standard queueing theoretical approach. In this study, by using the max-plus algebraic approach we studied buffer-shared fork-join production systems with general processing times. However, because it cannot provide proper computational ways for performance measures, we developed simulation models using @RISK software and the expressions derived from max-plus algebra. From the simulation experiments, we compared some properties on waiting time with respect to a buffer capacity under two blocking policies: BBS (Blocking Before Service) and BAS (Blocking After Service).

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.383-386
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• 2001

This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.