• Journal of Information Management
• /
• v.31 no.2
• /
• pp.31-46
• /
• 2000

This paper reviews the concept and structure of SICI and SISAC as a standardized serial format. The JST's LIRACS-II and KINITI's Library Information System are illustrated as an example of the automated serials check-in system using SISAC.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.34S no.8
• /
• pp.37-44
• /
• 1997

We implemented a code searcher which is used for the PN(pseudo noise) code acquisition in CDMA cellular mobile station. To reduce the reuired hardware and the code acquisition time, we used the double dwell structure which is an effective serial code acquisition metho. We designed a code acquisition has acquired within 1/2 PN chip range. The code searcher is implemented using 0.8 micron code searcher is successfully working in CDMA cellular mobile station and it satisfies the code acquisition time specified in IS-95 standard.

• Journal of Electrical Engineering and information Science
• /
• v.1 no.1
• /
• pp.98-107
• /
• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.68-73
• /
• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.35-42
• /
• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.17 no.1
• /
• pp.33-39
• /
• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.1152-1156
• /
• 2003

For pneumatic valve system control, we need a serial data transmission system with high speed and reliability for information interchange between main computer and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic valve system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid control valves. in addition, we developed a communication protocol for construction of rs-485 based multi-drop network and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. the field test results show that, even under high noise environment, the data transmission of 375kbps rate is possible up to 1,500meter without using repeater. In addition, the system developed in this research is easily to be extended for a communication network because of its modular structure.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2004.10a
• /
• pp.299-303
• /
• 2004

In our pervious paper, a new parallel-type spherical 3-degree-of-freedom mechanism consisting of a two-degree-of-freedom parallel module and a serial RRR subchain was proposed[1]. In this paper, its improved version is suggested and implemented. Differently from the previous 3-dof spherical mechanism, gear chains are incorporated into the current version of the mechanism to drive the distal revolute joint of the serial subchain from the base of the mechanism and in fact, the modification significantly improves kinematic characteristics of the mechanism within its workspace. Firstly, after a brief description on its structure, the closed-form solutions of both the forward and the reverse position analysis are derived. Secondly, the first-order kinematic model of the mechanism for the inputs which are assumed to be located at the base is derived. Thirdly, through the simulations of the kinematic analysis via. kinematic isotropic index, it is confirmed that the mechanism has much more improved isotropic properties throughout the workspace of the mechanism than the previous mechanism in [1]. Lastly, the proposed mechanism is implemented to verify the results from this analysis.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.53 no.12
• /
• pp.725-731
• /
• 2004

In this study, the three type hybrid interrupters according to the arrangement of the thermal expansion chamber and the puffer cylinder(they are called 'serial type', 'parallel/exchanged type', and 'parallel/separated type' respectively in this work) were designed and manufactured. This paper presents the tested results of the thermal recovery characteristics on the interrupters using a simplified synthetic test facility. The 'serial type' hybrid interrupter which is to obtain more easily the pressure rise for the thermal recovery compared with the others has the best capability in the thermal recovery characteristics. In order to investigate the stress on the operating mechanism, the distortion of the stroke wave in on-load test was examined to the stroke curve in no-load test. The biggest distortion was occurred in the 'parallel/exchanged type' hybrid interrupter. Finally, the small interruption capability on the three type interrupters was estimated by a theoretical form and the 'parallel/separated type' hybrid interrupter has the advantage of the others in the view of structure.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.165-168
• /
• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.