• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1087-1095
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• 2014

A recent major development in computer technology is the advent of the wearable computer system that is based on human-centric interface technology trends and ubiquitous computing environments. Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the IEEE 802.15.6 wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. And a communication structure that can differentiate QoS of U-health WBAN and WUSB traffic with different priorities is proposed for WUSB over IEEE 802.15.6 hierarchical protocol. In our proposal and performance evaluation, throughputs of U-health WBAN and WUSB traffic are analyzed under single and multiple QoS classes to evaluate the effectiveness of proposed QoS differentiating structure in WUSB over IEEE 802.15.6.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1619-1627
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• 2014

Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the IEEE 802.15.6 wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. And a communication structure that performs the time-synchronization is proposed for WUSB over IEEE 802.15.6 hierarchical protocol. Proposed time-synchronization mechanisms adopt the WBAN Polling Access and combine it with a time-synchronization middleware using time stamps. In our performance evaluations, time-synchronization performances with only WBAN Polling Access scheme are analyzed first. After that, performances combined with the time-synchronization middleware are analyzed to evaluate the effectiveness of proposed time-synchronization structure in WUSB over IEEE 802.15.6.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.267-273
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• 2009

In this paper, we proposed a variable average operation for a WDR(Wide Dynamic Range). The previously proposed average operation [5] improves hardware efficiency and complexity by replacing divider with multiplier. However, the previously proposed method has some weak-points. For example, there are counting horizontal and vertical length, and then the multiplier selects a Mode set by the user when the lengths exactly correspond with the image's size in the Mode. To compensate some weak-points, we change a Mode selection methods as a using the image's total size. Also, we propose another feature that it can be applied to various image sizes. To get a more accurate average, we add an external compensation value. We design the variable average operation using a Verilog-HDL and confirm that the Serial Multiplier's structure is better efficiency than Split Multiplier's structure.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.7
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• pp.63-72
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• 2019

The purpose of this study is to apply the types of urban street pattern and the shape of streets to the master plan of a religious community complexes. The street pattern is a framework of urban structure and to understand the urban structure is helpful to understand the nature of urban streets. By analysing the precedent researches, the types of street patterns are classified as a serial pattern, a branching pattern, a grid pattern and a web pattern. The street patterns are hierarchically composed and classified as a differential development and sequential development. There are boundaries and gates where the street space is differentiated to the more private level. The urban streets continue to the architectural streets such as arcades, deck streets, corridors, lobbies and halls. The purposes and results of the master plan of this religious community complexes are as follows. 1) The school area, housing area and service area are properly separated and connected. They are separated by the building masses and connected by the street space in between. 2) The street pattern of this complexes is a serial pattern where the streets are the center of each functional building groups. The entry square is divided by the symbolic building. The one branch is school street and the other is living street. These streets are combined again to the festival street. 3) The architectural streets are organically related to the urban streets. 4) Each street spaces are of adequate form according to its properties as a place. 5) There are boundaries or gates such as a gab between buildings, posts, arches and deck streets according to the relationship between streets.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.232-232
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• 2004

• Journal of Power Electronics
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• v.14 no.1
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• pp.194-201
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• 2014

To increase the capacity of secondary cells, an appropriate serial composition of the battery modules is essential. The unbalance that may occur due to the series connection in such a serial composition is the main cause for declines in the efficiency and performance of batteries. Various studies have been conducted on the use of a passive or active topology to eliminate the unbalance from the series circuit of battery modules. Most topologies consist of a complex structure in which the Battery Management System (BMS) detects the voltage of each module and establishes the voltage balancing in the independent electrical power converters installed on each module by comparing the module voltage. This study proposes a new magnetic flux sharing type DC/DC converter topology in order to remove voltage unbalances from batteries. The proposed topology is characterized by a design in which all of the DC/DC convertor outputs connected to the modules converge into a single transformer. In this structure, by taking a form in which all of the battery balancing type converters share magnetic flux through a single harmonic wave transformer, all of the converter voltages automatically converge to the same voltage. This paper attempts to analyze the dynamic properties of the proposed circuit by using a Programmable Synthesizer Interface Module (PSIM), which is useful for power electronics analysis, while also attempting to demonstrate the validity of the proposed circuit through experimental results.

• Journal of Biomedical Engineering Research
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• v.40 no.3
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• pp.116-124
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• 2019

The rehabilitation training robots for treating the upper limbs of stroke patients were mainly focused on the upper proximal treatment of it, but recently studies of the distal parts of the upper limbs for rehabilitation of the hand is making some progress even though it is still a small number so far. In this paper, we present the hand robot for the rehabilitation training of stroke patients that is the fingertip contact-typed mechanism, and it has also equipped with the wrist rehabilitation unit to be worked like human hand that enables any movements through mutual cooperation by fingers while picking up or grasping objects. The robot that is presented for this purpose supports the movement of fingers with 5-DoF and the wrist with 3-DoF that moves independently, and operates with a structure that allows the joints of the wrist and fingers to be collaborated organically together to each other. Also, hereby the simulation and evaluation test on its robot mechanism are performed to ensure that fingers with 5-DoF and the wrist with 3-DoF of the serial kinematical mechanism are designed to comply with or exceed ROM for ADL.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.161-166
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• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.