• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.837-842
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• 2010

In this paper, quantum cryptography systems used in the design process inevitably open bit stream of pseudo-random number that exists multiple open channels between them and the need to share information on the part of the situation exposes a pair of bit stream. In this paper, the base test of pseudo-random number I tested out this process and the merge bit binary column look out for randomness.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.10a
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• pp.40-47
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• 2000

One of the drawbacks of GA-based structural optimization is that the fitness evaluation of a population of hundreds of individuals requiring hundreds of structural analyses at each CA generation is computational too expensive. Therefore, a parallel genetic algorithm is developed for structural optimization on a cluster of personal computers in this paper. Based on the parallel genetic algorithm, a population at every generation is partitioned into a number of sub-populations equal to the number of slave computers. Parallelism is exploited at sub-population level by allocationg each sub-population to a slave computer. Thus, fitness of a population at each generation can be concurrently evaluated on a cluster of personal computers. For implementation of the algorithm a virtual distributed computing system in a collection of personal computers connected via a 100 Mb/s Ethernet LAN. The algorithm is applied to the minimum weight design of a steel structure. The results show that the computational time requied for serial GA-based structural optimization process is drastically reduced.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.3
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• pp.164-168
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies Horizontal Shuffle Scheduling (HSS) algorithm. In the result, number of iteration is half than conventional algorithm without performance degradation. Finally, this paper present design methodology of high-speed LDPC decoder and confirmed its throughput is up to about 600Mbps.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of Plant Biotechnology
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• v.33 no.1
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• pp.19-25
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• 2006

With the use of Agrobacterium and gene-gun, cold regulated gene (BN115) has been injected in Chrysanthemum leaf disc and transgenic plants have been produced successfully on the selection media containing phytohormone. To determine the presence of the transferred cold regulated gene (BN115) in the transgenic Chrysanthemum, PCR-amplification indicated the presence of that gene. Real-Time PCR for confirmation of the putative transgenic plants was established. The copy number of cold regulated gene (BN115) is extrapolated on the basis of a standard curve. Serial dilutions of known number of gene copies were in triplicates. In this diagram, PCR cycles are plotted against the fluorescence intensity. The cycle at which the fluorescence reaches a threshold cycle is inversely proportional to the starting amount of target DNA.

• The Journal of the Korean bone and joint tumor society
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• v.19 no.2
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• pp.50-55
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• 2013

Purpose: The purpose of this study is to determine the usefulness of arterial embolization on sacral and pelvic giant cell tumor (GCT). Materials and Methods: We retrospectively reviewed the medical records of 9 patients who had undergone serial arterial embolization between December 1996 and May 2008. We analyzed the clinical outcomes and therapeutic responsiveness of arterial embolization on sacral and pelvic GCT. Results: Six of 9 cases showed progression of disease (PD) status, even if 5 cases showed PD status despite of additional treatments including surgery and radiation, implying that serial arterial embolization on sacral and pelvic GCT is not effective. Three of 9 cases showed stable disease (SD) or continuous disease free (CDF) status and we analyzed associated factors with these good responses for embolization by ${\chi}^2$ test. The number of feeding vessels under six (p=0.048) and the number of collateral arterial supply under three (p=0.048) in the first angiogram showed significant relationships with good response for embolization, while remaining tumor staining by contrast after the first embolization and repeated embolization times were not significant. Conclusion: Although serial arterial embolization is not an effective modality on sacral and pelvic giant cell tumors, it may be a pilot modality under narrow indication of tumors with poor vascularity at first angiogram.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.15-26
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• 2005

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

• Korean Journal of Cognitive Science
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• v.15 no.3
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• pp.25-33
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• 2004

Two experiments were conducted to investigate the effects of two syntactic cues in pronoun referential resolution: number cue (plural or singular) and gender cue (unambiguous or ambiguous). Using self-paced sentence reading task for pronoun sentences and lexical decision task for antecedents, Experiment 1 showed that the reading time of a plural pronoun ('they') was faster than a singular pronoun ('he' or 'she'), but the lexical decision time did not differ with a number cue and a Bender cue. In Experiment 2, using RSVP for pronoun sentences and lexical decision task for antecedents, the results showed that the lexical decision time differed for a gender cue only. These results suggested that the syntactic cues of a pronoun influenced strongly on referential resolution in discourse comprehension.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.474-479
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• 2003

This paper addresses the problem of B-spline surface interpolation to serial contours, where the number of points varies from contour to contour. A traditional lofting approach creates a set of B-spline curves via B-spline curve interpolation to each contour, makes them compatible via degree elevation and knot insertion, and performs B-spline surface lofting to get a B-spline surface interpolating them. The approach tends to result in an astonishing number of control points in the resulting B-spline surface. This situation arises mainly from the inevitable process of progressively merging different knot vectors to make the B-spline curves compatible. This paper presents a new approach for avoiding this troublesome situation. The approach includes a novel process of getting a set of compatible B-spline curves from the given contours. The process is based on the universal parameterization [1,2] allowing the knots to be selected freely but leading to a more stable linear system for B-spline curve interpolation. Since the number of control points in each compatible B-spline curve is equal to the highest number of contour points, the proposed approach can realize efficient data reduction and provide a compact representation of a B-spline surface while keeping the desired surface shape. Some experimental results demonstrate its usefulness and quality.