• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.387-388
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• 2011

• 조명전기설비학회논문지
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• 제22권6호
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• pp.148-155
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• 2008

본 논문에서는 웨이퍼 에지 노광장비에 핵심 부분인 웨이퍼의 편심오차의 측정알고리즘과 플랫/노치의 방향을 해석하는 알고리즘을 제안하였다. 또한 새로 제안된 알고리즘을 전산 시뮬레이션을 통해 그 유효성을 확인하였으며 제작된 웨이퍼 에지 노광기에 적용하여 실제 장비에 적용 가능함을 확인하였다. 제안된 알고리즘을 위해 필요한 웨이퍼 에지 위치 검출방식에 있어 과거의 접촉식 방법을 사용함으로서 발생하는 파티클의 오염을 제거하기 위해 선형 CCD 센서를 적용한 비접촉 방식의 데이터 측정법을 적용함으로서 파티클의 오염을 제어 할 수 있었다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.3168-3172
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• 2007

As the minimum feature size decreases, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT and designed a particle deposition system which consists of scanning mobility particle sizer (SMPS) and deposition chamber. Charged monodisperse particles are generated using SMPS and deposited on the wafer by electrostatic force. The experimental results agreed with the simulation results well in terms of particle number and deposition area according to particle size, flow rate and deposition voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• 센서학회지
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• 제23권2호
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• 경영과학
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• 제31권3호
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• pp.27-39
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• 2014

We derive a generalized statistic form of Q control chart, which is especially suitable for short run productions and start-up processes, for the detection of process mean shifts. The generalization means that the derived control chart statistic concurrently uses within lot variability and between lot variability to explain the process variability. The latter variability source is noticeably prevalent in lot type production processes including semiconductor wafer fabrications. We first obtain the generalized Q control chart statistic when both the process mean and process variance are unknown, which represents the case of implementing statistical process control charting for short run productions and start-up processes. Also, we provide the corresponding generalized Q control chart statistics for the rest of three cases of previous Q control chart statistics : (1) both the process mean and process variance are known (2) only the process mean is unknown and (3) only the process variance is unknown.

• 반도체디스플레이기술학회지
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• 제15권4호
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• pp.67-72
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• 2016

In this study, the texturing and the emitter formation processes were carried out with the wafer adhesion method to increase the productivity and reduce the production cost of the multi-crystalline silicon solar cell. After fabricating $156{\times}156mm$ solar cell according to the wafer adhesion method, the operation characteristics were analyzed and compared with those of the solar cell fabricated by the standard process method. In the case of a solar cell formed by the wafer adhesion method, it showed Jsc of $32.87mA/cm^2$, Voc of 0.612V, FF of 78.04% and efficiency of 15.71% respectively. The efficiency of the solar cell formed by the wafer adhesion method was 0.1% higher than that of the solar cell formed by the standard method. In addition, the productivity of the texturing and the emitter formation processes is expected to be approximately doubled. Therefore, it is expected that the manufacturing cost of the multi-crystalline solar cell can be reduced due to the improved productivity compared with the standard process.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.197-201
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• 1997

To realize 10-Gbit/s optical transmission systems, we designed and fabricated a limiting amplifier with extremely high operation frequencies over 10-GHz using AlGaAs/GaAs heterojunction bipolar transistors (HBTs), and investigated their performances. Circuit design and simulation were performed using SPICE and LABRA. A discrete AlGaAs/GaAs HBT with the emitter area of 1.5${\times}$10$\mu\textrm{m}$$^2$, used for the circuit fabrication, exhibited the cutoff frequency of 63GHz and maximum oscillation frequency of 50GHz. After fabrication of MMICs, we observed the very wide bandwidth of DC∼15GHz for a limiting amplifier from the on-wafer measurement. Ceramic-packaged limiting amplifier showed the excellent eye opening, the output voltage swing of 750mV\ulcorner, and the rise/fall time of 40ps, measured at the data rates of 10-Gbit/s.

• Safety and Health at Work
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• 제10권3호
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• pp.347-354
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• 2019

Background: The aim of this study was to describe the types of diseases that developed in semiconductor workers who have registered with the Korea Workers' Compensation and Welfare Service (KWCWS) and to identify potential common occupational characteristics by the type of claimed disease. Methods: A total of 55 semiconductor workers with cancer or rare diseases who claimed to the KWCWS were compared based on their work characteristics and types of claimed diseases. Leukemia, non-Hodgkin lymphoma, and aplastic anemia were grouped into lymphohematopoietic (LHP) disorder. Results: Leukemia (n = 14) and breast cancer (n = 10) were the most common complaints, followed by brain cancer (n = 6), aplastic anemia (n = 6), and non-Hodgkin lymphoma (n = 4). LHP disorders (n = 24) accounted for 43%. Sixty percent (n = 33) of registered workers (n = 55) were found to have been employed before 2000. Seventy-six percent (n = 42) of registered workers and 79% (n = 19) among the registered workers with LHP (n = 24) were found to be diagnosed at a relatively young age, ${\leq}40years$. A total of 18 workers among the registered semiconductor workers were finally determined to deserve compensation for occupational disease by either the KWCWS (n = 10) or the administrative court (n = 8). Eleven fabrication workers who were compensated responded as having handled wafers smaller than eight inches in size. Eight among the 18 workers compensated (44 %) were found to have ever worked at etching operations. Conclusion: The distribution of cancer and rare diseases among registered semiconductor workers was closely related to the manufacturing era before 2005, ${\leq}8$ inches of wafer size handled, exposure to clean rooms of fabrication and chip assembly operations, and etching operations.

• 산업경영시스템학회지
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• 제35권1호
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• pp.79-86
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• 2012

This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.