• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.25 no.1
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• pp.36-44
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• 2015

Objectives: This study aimed to elucidate the physicochemical properties of silica powder and airborne particles as by-products generated from fabrication processes to reduce unknown risk factors in the semiconductor manufacturing work environment. Materials and Methods: Sampling was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. Thirty-two powder and airborne by-product samples, diffusion(10), chemical vapor deposition(10), chemical mechanical polishing(5), clean(5), etch process(2), were collected from inner chamber parts from process and 1st scrubber equipment during maintenance and process operation. The chemical composition, size, shape, and crystal structure of silica by-product particles were determined by using scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy, and x-ray diffractometry. Results: All powder and airborne particle samples were composed of oxygen(O) and silicon(Si), which means silica particle. The by-product particles were nearly spherical $SiO_2$ and the particle size ranged 25 nm to $50{\mu}m$, and most of the particles were usually agglomerated within a particle size range from approximately 25 nm to 500 nm. In addition, the crystal structure of the silica powder particles was found to be an amorphous silica. Conclusions: The silica by-product particles generated from the semiconductor manufacturing processes are amorphous $SiO_2$, which is considered a less toxic form. These results should provide useful information for alternative strategies to improve the work environment and workers' health.

• Journal of the Semiconductor & Display Technology
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• v.3 no.2
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• pp.5-9
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• 2004

Microcircuit fabrication requires precise control of impurities in tiny regions of the silicon. These regions must be interconnected to create components and VLSI circuits. The patterns to define such regions are created by lithographic processes. In order to image features smaller than 70 nm, it is necessary to employ non-optical technology (or next generation lithography: NGL). One such NGL is extreme ultra-violet lithography (EUVL). EUVL transmits the pattern on the wafer surface after reflecting ultra-violet through mask pattern. If particles exist on the blank mask, it can't transmit the accurate pattern on the wafer and decrease the reflectivity. It is important to care the blank mask. We removed the particles on the wafer using focused ion beam (FIB). During removal, FIB beam caused damage the multi layer mask and it decreased the reflectivity. The relationship between particle removal and reflectivity is examined: i) transmission electron microscope (TEM) observation after particle removal, ii) reflectivity simulation. It is found that the image mode of FIB is more effective for particle removal than spot and bar mode.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Safety and Health at Work
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• v.9 no.3
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• pp.249-256
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• 2018

This article aims to provide a systematic review of the exposure assessment methods used to assign wafer fabrication (fab) workers in epidemiologic cohort studies of mortality from all causes and various cancers. Epidemiologic and exposure-assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until 2017. The studies found various outcomes possibly linked to fab operations, but a clear association with the chemicals in the process was not found, possibly because of exposure assessment methodology. No study used a tiered assessment approach to identify similar exposure groups that incorporated manufacturing era, facility, fab environment, operation, job and level of exposure to individual hazardous agents. Further epidemiologic studies of fab workers are warranted with more refined exposure assessment methods incorporating both operation and job title and hazardous agents to examine the associations with cancer risk or mortality.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.161-166
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• 2003

Semiconductor Manufacturing has emerged as one of the most Important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.5
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• pp.350-355
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• 2000

The fabrication of sapphire wafer in C plane has been developed by horizontal Bridgeman method and GaN based semiconductor epitaxial growth has been carried out in metal organic chemical vapour deposition. The single crystalline ingot of sapphire has been utilized for 2 inch sapphire wafers and wafer slicing and lapping machines were designed. These several steps of lapping processes provided the mirror-like surface of sapphire wafer. The measurements of the surface flatness and the roughness were carried out by the atomic force microscope. The GaN thin film growth on the developed wafer was confirmed the wafer quality and applicability to blue light emitting devices.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.183-187
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• 2005

Thin films of diblock copolymers may be suitable for semiconductor device applications since they enable patterning of ordered domains with dimensions below photolithographic resolution over wafer-scale area. We obtained nanometer-scale cylindrical structure of dibock copolymer of polystyrene-block-poly(methylmethacrylate), PS-b-PMMA, also demonstrate pattern transfer of the nanoporous polymer using both reactive ion etching. The size of fabricated naonoholes were about 10 nm. Fabricated nanopattern surface was observed by field emission scanning electron microscope (FESEM).