• Title/Summary/Keyword: Semiconductor test equipment

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Implementation of Memory controller for Punctuality Guarantee from Memory-Free Inspection Equipment using DDR2 SDRAM (DDR2 SDRAM을 이용한 비메모리 검사장비에서 정시성을 보장하기 위한 메모리 컨트롤러 구현)

  • Jeon, Min-Ho;Shin, Hyun-Jun;Kang, Chul-Gyu;Oh, Chang-Heon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.136-139
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    • 2011
  • The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

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A Study on the Vibration Criteria Decision for High Technology Facilities using FRF (주파수 응답함수를 이용한 고정밀 장비의 진동허용규제치 결정기법에 관한 연구)

  • 이홍기;김두훈;김사수
    • Journal of KSNVE
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    • v.6 no.3
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    • pp.363-373
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    • 1996
  • In the case of a precision equipment, it requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga class semiconductor wafers. This high technology equipments require very strict environmental vibration standard in promotion to the accuracy of the manufacturing, inspecting devices. The vibration criteria are usually obtained either by the real vibration exciting test on the equipment or by the analytical calculation. The former is accurate but requires a great deal of time and efforts while the latter lacks reliability. This paper proposes a new method to solve this problem at a time. The permissible vibration level to a precision equipment can be easily obtained by analyzing the process of Frequency Response Function(FRF). This paper also demonstrates its effectiveness by applying the proposed method to finding the permissible vibration criteria of a Computer Hard Disk Drive.

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Development of Smart ICT-Type Electronic External Short Circuit Tester for Secondary Batteries for Electric Vehicles (전기자동차용 2차전지를 위한 스마트 ICT형 전자식 외부 단락시험기 개발)

  • Jung, Tae-Uk;Shin, Byung-Chul
    • Journal of the Korean Society of Industry Convergence
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    • v.25 no.3
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    • pp.333-340
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    • 2022
  • Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.

A Study on the Semiconductor Wastewater Treatment and Recycling by VSEP system (진동막분리장치에 의한 반도체폐수처리와 재이용에 관한 연구)

  • Kang Gyung-Hwan
    • Journal of Environmental Science International
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    • v.14 no.3
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    • pp.335-343
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    • 2005
  • The objective of this research is to evaluate a feasibility of wastewater reuse by membrane treatment with vibrating membrane separation equipment. Molecular weight of compounds in wastewater, permeability of membrane and retentate characterization after membrane filtration were investigated in order to determine appropriate membrane pore size and materials for wastewater treatment. Selected membrane was evaluated with vibration membrane separation equipment to optimize operating conditions. The following conclusion are drawn. 1. We got as following test results after the distribution of particles in the semiconductor wastewater, are made up of $1\~20{\mu}m$. Si, gold and Al in turn are contained in semiconductor wastewater. 2. Recovery rate is changeless under increasing recovery rate in operation. Though a value can be if pressure can be changed, the highest value of permeate rate is presented in 150 psi. 3. The AS-100(polysulpone) was selected as the most appropriate membranes for the treatment of semi-conductor wastewater to VSEP system. The fouling almost did not occur during this experiments. The analyses of treated water with VSEP system showed conductivity: 0.059,us/cm, TDS: 40mg/l, COD: 20mg/l, SS : 5mg/l, n-Hexane: 8.3mg/l. Comparing previous systems, operating expenses is decreased by more $50\%$.

Long Life Design of SSD Test Gender by Reducing Ejecting Force (인출력 저감을 통한 SSD Test Gender의 장수명 설계)

  • Kim, Jae Kyung;Park, Hyung Suk;Lee, Ki Seok;Jeon, Euy sik
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.4
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    • pp.139-144
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    • 2020
  • Recently, the electronic equipment industry has become active due to the continuous increase in portable storage media with high-speed information communication, and in particular, the production of SSD(Solid State Drives) for miniaturization of mobile devices and high-speed information communication has increased rapidly. When the SSD is ejecting in the SSD test gender, the necessary ejecting force must be kept constant to have a lifespan applicable to the test device. When the ejecting force increased, it leads to wear of the link for ejecting, which causes a problem in that repeated durability decreases and the ejecting of the SSD becomes impossible. In this paper, the repeated durability test analysis according to the material and the reducing ejecting force design were performed to increase the life of the test gender for SSD inspection. The wear level of the pusher head and ejector was analyzed through repeated durability tests according to the material of the pusher head. The validity of the design was verified through the ejecting force test and repeated durability test of the Test gender, which was designed by carrying out the design to reduce the size and ejecting force of the test gender.

Implementation of Exposure Stage Integrated Control System for FPD (FPD용 노광 스테이지의 통합 제어시스템 구현)

  • Kim, Jong-Won;Seo, Jae-Yong;Cho, Hyun-Chan;Cho, Tai-Hoon;Kang, Heung-Seok
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.4 s.17
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    • pp.11-15
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    • 2006
  • Expose equipment system that is used for manufacturing process of Flat Panel Display, is most important equipment in whole process. Expose equipment that is for making pattern of mask on substrate, consists of optical part, stage part and transport part. The stage is an important part that aligns mask and substrate for delivering pattern of mask to substrate exactly. In this paper, control system of expose stage that is able to use mask and substrate of diverse size, with PC controller using GUI interface instead of PLC control system. The existing PLC control system does not have the suitable structure for using mask of diverse size. GUI interface integration control system is based on PC. So it has the advantage of convenient use and active operation. We embodied PLC control system in integration control system based on PC, and verified utility possibility through the standard test course.

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NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors

  • Kim, Gyu-Yeol;Nah, Wansoo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.641-649
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    • 2016
  • In this paper, a novel time-domain measurement technique on a high parallelism probe card with protection resistors installed is proposed. The measured signal amplitude decreases when the measurement is performed by Needle Auto Calibration (NAC) probing on a high parallelism probe card with installed resistors. Therefore, the original signals must be carefully reconstructed, and the compensation coefficient, which is related to the number of channel branches and the value of protection resistors, must be introduced. The accuracy of the reconstructed signals is analyzed based on the varying number of channel branches and various protection resistances. The results demonstrate that the proposed technique is appropriate for evaluating the overall signal performance of probe cards with Automatic Test Equipment (ATE), which enhances the efficiency of probe card performance test dramatically.

New Mechanism for Wafer Guide to Minimize the Drop in Wafer Transfer (반송 시 웨이퍼 이탈을 최소화 하기 위한 새로운 형태의 웨이퍼 가이드 메커니즘)

  • Kim, Dea-Won;Ryu, Jee-Hwan
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.1
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    • pp.23-28
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    • 2010
  • In this paper, wafer drop from wafer guide mechanism, which is one of the serious problems in water transfer robot, is analyzed, and new wafer guide mechanisms are proposed to minimize this drop. Three types of new wafer guide mechanisms are proposed: roller type, gear type and L-shape rocker type. We choose one of the proposed mechanism, which is roller type, and verified this mechanism through real transfer experiment. Wafer picking up test is conducted with initial aligning error for simulating the wafer drop. Number of drop is compared between conventional mechanism and proposed mechanism. As a result, we can find the proposed mechanism can reduce the number of wafer drop dramatically.

레이저를 이용한 웨이퍼 다이싱 특성 분석

  • Lee Yong-Hyeon;Choe Gyeong-Jin;Yu Seung-Ryeol;Yang Yeong-Jin;Bae Seong-Chang
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2006.05a
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    • pp.251-254
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    • 2006
  • In this paper, cutting qualifies and fracture strength of silicon dies by laser dicing are investigated. Laser micromachining is the non-contact process using thermal ablation and evaporation mechanisms. By these mechanisms, debris is generated and stick on the surface of wafer, which is the problem to apply laser dicing to semiconductor manufacture process. Unlike mechanical sawing using diamond blade, chipping on the surface and crack on the back side of wafer isn't made by laser dicing. Die strength by laser dicing is measured via the three-point bending test and is compared with the die strength by mechanical sawing. As a results, die strength by the laser dicing shows a decrease of 50% in compared with die strength by the mechanical sawing.

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Study on the Sensor Development for Liquid Contamination during Delivery (이송 중 액체오염 검출센서 개발에 관한 연구)

  • Jeong, Yi Ha;Kim, Byung Han;Hong, Joo-Pyo
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.2
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    • pp.70-73
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    • 2016
  • Previously proposed contamination detecting sensor was revisited for the investigation of the liquid tendency. Experiments revealed different output voltages for several kinds of liquid input, but showed same values for various flow rates of each liquid. The transmittance of the liquid was measured, and it is well correlated with the voltages. Linearity in values and the compensation of the sensor to sensor deviation were tried to obtain. And, long term test was performed as attached at the manufacturing equipment in the field.