• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.136.2-136.2
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• 2015

반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

• Design & Manufacturing
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• v.7 no.1
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• pp.55-59
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• 2013

A Light Emitting Diode(LED) is a semiconductor device which converts electricity into light. LEDs are widely used in a field of illumination, LCD(Liquid Crystal Display) backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. In general, LEDs production does die bonding and wire bonding on board, and do silicon and phosphor dispensing to protect LED chip and improve brightness. Then lens molding process is performed using mixed liquid silicon rubber(LSR) by resin and hardener. A mixture of resin and hardener affect the optical characteristics of the LED lens. In this paper, computational design of static mixer was performed for mixing of liquid silicon. To evaluate characteristic of mixing efficiency, finite element model of static mixer was generated, and fluidic analysis was performed according to length of mixing element. Finally, optimal condition of length of mixing element was applied to static mixer from result of fluidic analysis.

• Proceedings of KOSOMES biannual meeting
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• 2005.11a
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• pp.197-202
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• 2005

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection using subpixel edge detection method in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.451-459
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• 2007

RFID it reads information which is it writes, the semiconductor chip for and the radio frequency system which uses the hazard antenna it has built-in transmission of information it talks. Formation which is transmitted like this collection and America which it filtrates wey the RFID search service back to inform the location of the server which has commodity information which relates with an object past record server. The hazard where measurement analysis result the leader for electronic interference does not occur consequently together from with verification test the power level which is received from the antenna grade where it stands must maintain minimum -55dBm and the electronic interference will not occur with the fact that, antenna and reel his recognition distance the maximum 7m until the recognition which is possible but smooth hazard it must stand and and with the fact that it will do from within and and and 3-4m it must be used Jig it is thought.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.239-244
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• 1998

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin film have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. Surface micromachining techniques have been applied in a GaAs MESFET process to form both microsensors and electronic circuits. The on-chip integration of microsensors such as pressure sensors and infrared detectors with GaAs integrated circuits is attractive because of the higher operating temperature up to 200 oC for GaAs devices compared to 125 oC for silicon devices and radiation hardness for infrared imaging applications. The microsensors incorporate a 1${\mu}$m-thick sputtered ZnO capacitor supported by a 2${\mu}$m-thick aluminum membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of an area 80${\times}$80 ${\mu}$m2 designed for use as a miniature microphone exhibits 2.99${\mu}$V/${\mu}$ bar sensitivity at 400Hz. The voltage responsivity and the detectivity of a single infrared detector of an area 80${\times}$80 $\mu\textrm{m}$2 is 700 V/W and 6${\times}$108cm$.$ Hz/W at 10Hz respectively, and the time constant of the sensor with the amplifying circuit is 53 ms. Circuits using 4${\mu}$m-gate GaAs MESFETs are fabricated in planar, direct ion-implanted process. The measured transconductance of a 4${\mu}$m-gate GaAs MESFET is 25.6 mS/mm and 12.4 mS/mm at 27 oC and 200oC, respectively. A differential amplifier whose voltage gain in 33.7 dB using 4${\mu}$m gate GaAs MESFETs is fabricated for high selectivity to the physical variable being sensed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.726-729
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• 2010

Copper Pillar Tin Bump (CPTB) was investigated for high density chip interconnect technology development, which was prepared by electroplating and electro-less plating methods. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM-1250 dry film photoresist (DFR), with copper electroplating for Copper Pillar Bump (CPB) formation firstly, and then tin electro-less plating on it for control oxidation. Electric resistivity and mechanical shear strength measurements were introduced to characterize the oxidation effects and bonding process as a function of thermo-compression. Electrical resistivity increased with increasing oxidation thickness, and shear strength had maximum value with $330^{\circ}C$ and 500 N thermo-compression process. Through the simulation work, it was proved that when the CPTB decreased in its size, it was largely affected by the copper oxidation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.23-30
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• 2007

RFID it reads information which is it writes, the semiconductor chip for and the radio frequency system which uses the hazard antenna it has built-in transmission of information it talks. Formation which is transmitted like this collection and America which it filtrates wey the RFID search service back to inform the location of the server which has commodity information which relates with an object past record server. The hazard where measurement analysis result the leader for electronic interference does not occur consequently together from with verification test the power level which is received from the antenna grade where it stands must maintain minimum -55dBm and the electronic interference will not occur with the fact that, antenna and reel his recognition distance the maximum 7m until the recognition which is possible but smooth hazard it must stand and and with the fact that it will do from within and and and 3-4m it must be used Jig it is thought.