• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.15-21
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• 2013

In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of Magnetics
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• 제16권3호
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• pp.234-239
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• 2011

Transcranial magnetic stimulation utilizes the method of controlling applied time and changing pulse by output pulse through power density control for diagnosis purposes. Transcranial magnetic stimulation can also be used in cases where diagnosis and treatment are difficult since output pulse shape can be changed. As intensity, pulse range, and pulse shape of the stimulation pulse must be changed according to lesion, the existing sine wave-shaped stimulation treatment pulse poses limitations in achieving various treatments and diagnosis. This study actualized a new method of transcranial magnetic stimulation that applies a 3 Stage 2 Switch( power semiconductor 2EA) for controlling pulse repetition rate by achieving numerous switching control of stimulation coil. Intensity, pulse range, and pulse shape of output can be freely changed to transform various treatment pulses in order to overcome limitations in stimulation treatment presented by the previous sine wave pulse shape. The method of freely changing pulse range by using 3 Stage 2 Switch discharge method is proposed. Pulse shape, composed of various pulse ranges, was created by grafting PFN (Pulsed Forming Network) through AVR AT80S8535 one-chip microprocessor technology, and application in transcranial magnetic stimulation was achieved to study the output characteristics of stimulation treatment pulse according to delaying time of the trigger signal applied in section switch.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권3호
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• pp.91-95
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• 2004

The pulsed power system is widely available for use in pulse generator applications. Generally, the pulse generator is required for very short pulse width and high peak value. We have designed and fabricated our own pulsed type power system and through its use, we investigated microbe removal characteristics. This paper introduces a simple pulsed power system for removing various microbes caused by dirty water. This system includes a 2 times power supply circuit, IR2110 operated by using a fixed voltage regulator 7812 and 7805, and the switching MOSFET (Metal Oxide Semiconductor Field Effect Transistor). We can also control this process by using a PIC one chip microprocessor. As a result, we can obtain good removing characteristics of various microbes by adjusting the charging voltage, the pulse repetition rate and the electrical field inducing time.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.768-770
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• 2010

현대의 반도체기술은 매우 발전하여 FPGA에 주문형 반도체 기능회로를 집적할 수 있는 차원을 넘어 마이크로프로세서 기반의 시스템온칩을 설계할 수 있는 형태로 발전하였다. Xilinx 사의 SPARTAN-3E는 50만 게이트 급의 FPGA를 사용하며 소프트 코어 형태의 마이크로블레이즈(MicroBlaze) 프로세서를 사용하여 주변기기를 설계할 수 있는 버스 시스템을 갖추고 있다. 본 논문에서는 이러한 FPGA 시스템을 사용하여 간단한 마이크로콘트롤러 형태의 임베디드 시스템을 구현하는 방법에 대하여 논하고, 주변기기와 버스 프로토콜을 소개하고 이러한 형태의 임베디드 시스템의 확장성에 대해 논의한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.571-572
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• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.

• 대한의용생체공학회:의공학회지
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• 제17권4호
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• pp.499-506
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• 1996

Blood flow velocimeter is an essential device to measure the blood flow in skin tissue. In this study, we developed a high-speed LDV(laser Doppler Velocimeter) that has real time processing capability using a DSP(digital signal processing) chip and is able to continuously measure information about blood-flow based on a noninvasive method using self-mixing type laser diode. This LDV system has a simpler structure than any other typical blood flow velocimeter and is composed of new self-mixing probe, stabilizer circuits DSP board, and interf'ace boule We measured velocity of speaker-unit by operational frequencies to identify Doppler effect of this system, performed clinical experiment on bare finger tip and compared it with a commercial euipment BPM403A(USA).

• 대한안전경영과학회지
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• 제17권3호
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• 한국컴퓨터정보학회논문지
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• 제23권1호
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• 한국정보전자통신기술학회논문지
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• 제12권2호
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.