• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.114-126
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• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.34-41
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• 2001

Semiconductors performing digital clocking are a main source of radiated emission noise. Therefore, the most secure method of reducing emission noise is to reduce emission radiated from semiconductors; an application of an absorber to the surface of semiconductors is one of these methods, too. However, in reality, it is difficult to achieve as much effect of noise reduction as expected by using only absorber. It is confirmed by experiment in this paper that a loop area within chip has no correlation with radiated emission noise and it is clarified why the existing absorber fails to achieve a satisfactory effect of emission noise reduction. Besides, a new type of chip coating absorber has been developed which can cover up to semiconductor out lead by using ferrite coating material of ferrite/epoxy acrylate substance using only permeability loss out of electromagnetic wave reduction characteristics of materials. As a result of evaluating radiated emission noise by applying this coating absorber to semiconductor device, it could be confirmed that emission noise decreased from about 3 ㏈ up to 20㏈ depending on frequency.

• Electronics and Telecommunications Trends
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• v.37 no.2
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• pp.62-72
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• 2022

AMD is an American fabless semiconductor company that designs CPUs, GPUs, FPGAs, and APUs. AMD is competing with Intel with its Ryzen CPUs and Nvidia with its Radeon GPUs. Since 2008, production has been consigned to TSMC, concentrating on semiconductor design. AMD is releasing various new products through continuous R&D which is the basis for its growth. AMD stock have recorded the highest rise among global semiconductor companies as sales and operating profit soared due to the strong sales of new products.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.120-126
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• Journal of Information Display
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• v.3 no.2
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• pp.1-5
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• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1509-1514
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• 2011

The core of IT products, electronic components, especially the MLCC, chip inductors, chip Varistors and so on. In order to test the electrical characteristics of the chip using the Reno-pin contact test method has been used. In current chips, mass production of semiconductor manufacturing processes, high-speed production test for the chip speed up, precision is required. But Vibration displacement is a very short, so in order to overcome these shortcomings, the displacement amplification to design the structure has been actively studied. In this paper, a building structure with a flexible hinge was designed amplification instrument, semiconductor chip industry in the performance test and inspection equipment to measure the electrical characteristics of high speed linear actuators Reno-Pin using system was developed.