• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• Korean Journal of Metals and Materials
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• v.46 no.5
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.500-506
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• 1999

We designed and fabricated a bidirectional optical transceiver module for low cost access network. An integrated chip forming a pin-PD on an 1.3 urn FP-LD was assembled by flip-chip bonding on a Si optical bench, a single mode fiber with an angled end facet was aligned passively with the integrated chip on V-groove of Si-optical bench. Gaussian beam theory was applied to evaluate the coupling coefficients as a function of some parameters such as alignment distance, angle of fiber end facet, vertical alignment error. The theory is also used to search the bottle-neck between transmittance and receiving coupling efficiency in the bi-directional optical system. Tn this paper, we confirmed that reduction of coupling efficiency by the vertical alignment error between laser beam and fiber core axis can be compensated by controlling the fiber facet angle. In the fabrication of sub-module, a'||'&'||' we made such that the fiber facet have a corn shape with an angled facet only core part, the reflection of transmitted laser beam from the fiber facet could be minimized below -35 dE in alignment distance of 2: 30 /J.m. In the same condition, transmitted output power of -12.1 dEm and responsivity of 0.2. AIW were obtained.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.602-605
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• 2000

Recently, a study of intellectual smell recognition system is applied for the various fields such as control of food processing and survey of decay. A basic gas recognition system was implemented gases using four metal oxides semiconductor sensors as inputs. A CPLD chip of twenty thousand gates level was used for this purpose. The CPLD chip was designed and the availability of the one chip smell recognition system was tested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.422-424
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• 2009

In this paper, we studied methods that measure chip stack height using slit beam in mold equipment among semiconductor manufacture equipments. We studied two methods to improve chip stack height measurement performance. First, it is relation of camera exposure time and height measurement repeatability. Second we could improve measurement performance applying method of least mean square method for measurement error minimization about PCB(Printed Circuit Board) flexure phenomenon.

• Korean Management Science Review
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• v.18 no.1
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• pp.1-13
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• 2001

Despite that the semiconductor industry plays an important role to our economy, it has abnormal industrial structure stressing too much on memory chips. Thus, it is essential for our corporate to develop nonmemory chips to obtain technological leadership in a highly competitive semiconductor market. In this study, we demonstrate how benefit/cost analysis using the Analytic Hierarchy process (AHP) can be used for the proper selection of nonmemory semiconductor chips: Microprocessor, ASIC, digital IC and Analogue IC. The final results show that ASIC is the most attractive chip to develop, followed by Analogue IC, digital IC and Microprocessor. This is Somewhat consistent with the information that we found with respect to the elements that were taken into consideration. Sensitivity analysis is also provided here.