• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.552-560
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• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.556-561
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• 2013

Interest in spin-torque oscillators (STOs) has been increasing due to their potential use in communication devices. In particular the magnetic tunnel junction-based STO (MTJ-STO) with high perpendicular anisotropy is gaining attention since it can generate high output power. In this paper, a circuit-level model for an in-plane magnetized MTJ-STO with partial perpendicular anisotropy is proposed. The model includes the perpendicular torque and the shift field for more accurate modeling. The bias voltage dependence of perpendicular torque is represented as quadratic. The model is written in Verilog-A, and simulated using HSPICE simulator with a current-mirror circuit and a multi-stage wideband amplifier. The simulation results show the proposed model can accurately replicate the experimental data such that the power increases and the frequency decreases as the value of the perpendicular anisotropy gets close to the value of the demagnetizing field.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.793-799
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• 2016

A multi-purpose sensor interface that provides dual-mode operation of fingerprint sensing and physiological signal detection is presented. The dual-mode sensing capability is achieved by utilizing inter-pixel shielding patterns as capacitive amplifier's input electrodes. A prototype readout circuit including a fingerprint panel for feasibility verification was fabricated in a $0.18{\mu}m$ CMOS process. A single-channel readout circuit was implemented and multiplexed to scan two-dimensional fingerprint pixels, where adaptive calibration capability against pixel-capacitance variations was also implemented. Feasibility of the proposed multi-purpose interface was experimentally verified keeping low-power consumption less than 1.9 mW under a 3.3 V supply.

• 센서학회지
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• 제8권2호
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• pp.108-114
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• 1999

표면 탄성파 가스센서는 소자의 크기가 작고, 값이 싸며, 가스에 대한 감도가 매우 높고 소자의 신뢰도가 높은 장점을 갖고 있다. 본 연구에서는, $LiTaO_3$ 단결정 압전기판 위에 이중지연선을 갖는 표면 탄성파 $NO_2$ 가스센서를 설계 및 제작하였다. 제조된 IDT의 커패시턴스는 79.3MHz의 주파수에서 326.34pF였다. 임피던스 매칭이 된 IDT의 반사손실은 79.3MHz의 주파수에서 최대인 -16.74dB로 나타났다. SAW 발진기를 성하여 고주파증폭기의 이득을 적절히 조정함으로써 안정된 발진이 이루어짐을 확인하였다. SAW 발진기의 $NO_2$ 가스에 대한 발진주파수의 변이는 28Hz/ppm으로 나타났다.

• Journal of the Optical Society of Korea
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• 제13권3호
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• pp.330-334
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• 2009

A simple and compact frequency swept laser is demonstrated at $1.3{\mu}m$ using a wavelength scanning filter based on a rotating slit disk. The laser is comprised of a pigtailed semiconductor optical amplifier, a circulator, and a wavelength scanning filter in an extended cavity configuration. The wavelength scanning filter is composed of a collimator, a diffraction grating, a rotating slit disk, and a mirror. The instantaneous laser output power is more than 5 mW. The scanning range of the laser is extended to 80 nm at the maximum level, and 55 nm in the full width at half maximum at a scanning rate of 2 kHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.733-740
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• 2014

A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 mV / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be $268{\mu}V_{rms}$ in 0.5 Hz to 50 Hz, which is 41.2% smaller than conventional CTIA.

• 한국통신학회논문지
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• 제21권7호
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• pp.1850-1860
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• 1996

We present the results for the design ofantireflection (AR) coatings on facets of a multilayered structure waveguide device. The method, whose results agree very well with the reusults of the rigorous method in the case of a symmetric three layer structure deveice, is extended for the design of AR coatings on the facets of a multilayered structure waveguide device. the field profile in a multilayered structure waveguide necessary for the use of the extended method is obtained from the transfer matrix method. The virtual four layered structure method (VFLM) is proposed to reduce the time for the design ofAR coatings because the time for the design of AR coatings using the extended method increases as the number of layers increases. The optimum coating parameters and tolerance mapsfor two different six layered waveguide devices in Ref. [9] and [10] are obtained using the extendedmethod and the VFLM,and for the three different cases approximated as three layered waveguide devices to compare the results of each case. The results of the VFLM are similar to those of the extended methodcompared to those of the three layered structure waveguide. The main reason for the above results is that the field profile in the device calculated usingthe VFLM is similar to that calculated using the extended method compared to that for three layered structure wavegjide. We conclude that the extended method or VFLM should be used for the design of AR coatings on facets of a deice required for the facet reflectivity less than 10$^{-3}$ such as a semiconductor otical amplifier.