• International Journal of Quality Innovation
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• v.8 no.1
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• pp.137-153
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• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.68-72
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• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• Journal of the Semiconductor & Display Technology
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• v.3 no.2
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• pp.23-26
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• 2004

Thin film is one of the most general structures used in micro-electro-mechanical systems (MEMS). To measure the mechanical properties of SU-8 film, tensile testing was adopted which offers not only elastic modulus but also yield strength and plastic deformation by load-displacement curve. Tensile testing system was constructed with linear guided servo motor for actuation, load cell for force measurement and dual microscope for strain measurement.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.111-121
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• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.2
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• pp.81-86
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• 2005

This paper proposes a non-destructive ESPI technique to quantitatively evaluate defects inside a semiconductor package. The inspection system consists of the ESPI system, a thermal loading system and an adiabatic chamber. The technique is high feasibility for non-destructive testing of a semiconductor and overcomes the weaknesses of previous techniques, such as time-consumption and difficult quantitative evaluation. Most defects are classified as delamination defects, resulting from the insufficient adhesive strength between layers and from non-homogeneous heat spread. Ninety percent of the tested samples had delamination defects which originated at the corner of the chip and nay be related to heat spread design.

• Journal of Mechanical Science and Technology
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• v.19 no.3
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• pp.820-825
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• 2005

This paper proposes non-destructive ESPI technique to evaluate inside defects of semiconductor package quantitatively. Inspection system consists of ESPI system, thermal loading system and adiabatic chamber. The technique has high feasibility in non-destructive testing of semiconductor and gives solutions to the drawbacks in previous technique, time-consuming and the difficulty of quantitative evaluation. In result, most of defects are classified in delamination, from which it is inferred to the insufficiency of adhesive strength between layers and nonhomogeneous heat spread. The $90\%$ of tested samples have a delamination defect started at the around of the chip which may be related to heat spread design.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.124-128
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• 2023

Semiconductor engineers have long sought to enhance the energy efficiency of mobile semiconductors by reducing their voltage. During the final stages of the semiconductor manufacturing process, the screening and evaluation of voltage is crucial. However, determining the optimal test start voltage presents a significant challenge as it can increase testing time. In the semiconductor manufacturing process, a wealth of test element group information is collected. If this information can be controlled to predict the test voltage, it could lead to a reduction in testing time and increase the probability of identifying the optimal voltage. To achieve this, this paper is exploring machine learning techniques, such as linear regression and ensemble models, that can leverage large amounts of information for voltage prediction. The outcomes of these machine learning methods not only demonstrate high consistency but can also be used for feature engineering to enhance accuracy in future processes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.699-708
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• 1990

This paper proposes two test procedures for detecting functional faults in semiconductor random access memories (RAM's) and a new testimg scheme to execute the proposed test procedures. The first test procedure detects stuck-at faults, coupling faults and decoder faults, and requires 19N operations, which is an improvement over conventional procedures. The second detects restricted patternsensitive faults and requires 69N operations. The proposed scheme uses Built-In Self Testing (BIST) techniques. The scheme can write into more memory cells than I/O pins can in a write cycle in test mode. By using the scheme, the number of write operations is reduced and then much testing time is saved.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.