• International Journal of Quality Innovation
• /
• 제8권1호
• /
• pp.137-153
• /
• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• 반도체디스플레이기술학회지
• /
• 제19권3호
• /
• pp.68-72
• /
• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• 반도체디스플레이기술학회지
• /
• 제3권2호
• /
• pp.23-26
• /
• 2004

Thin film is one of the most general structures used in micro-electro-mechanical systems (MEMS). To measure the mechanical properties of SU-8 film, tensile testing was adopted which offers not only elastic modulus but also yield strength and plastic deformation by load-displacement curve. Tensile testing system was constructed with linear guided servo motor for actuation, load cell for force measurement and dual microscope for strain measurement.

• 전자공학회논문지A
• /
• 제31A권8호
• /
• pp.111-121
• /
• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• 대한산업공학회지
• /
• 제41권3호
• /
• pp.267-274
• /
• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• 비파괴검사학회지
• /
• 제25권2호
• /
• pp.81-86
• /
• 2005

본 논문에서는 반도체 패키지 내부결함의 비파괴 정량평가를 위한 ESPI 기법을 이용한 시스템 및 검사기 법을 제안하고 있으며, 검사시스템은 ESPI 검사장치, 열변형유도장치, 단열챔버로 구성되어있다. 기존 초음파, X-ray 기반의 검사기법에 비하여 측정시간 및 검사방법이 용이하며, 결함의 정량검출이 가능하다는 장점이 있다. 검사결과에서 대부분의 결함이 열 방출이 많은 칩 주위에서 박리결함으로 나타났으며, 원인은 층간 접착강도의 약화와 열분배 설계에서 문제점인 것으로 사료된다.

• Journal of Mechanical Science and Technology
• /
• 제19권3호
• /
• pp.820-825
• /
• 2005

This paper proposes non-destructive ESPI technique to evaluate inside defects of semiconductor package quantitatively. Inspection system consists of ESPI system, thermal loading system and adiabatic chamber. The technique has high feasibility in non-destructive testing of semiconductor and gives solutions to the drawbacks in previous technique, time-consuming and the difficulty of quantitative evaluation. In result, most of defects are classified in delamination, from which it is inferred to the insufficiency of adhesive strength between layers and nonhomogeneous heat spread. The $90\%$ of tested samples have a delamination defect started at the around of the chip which may be related to heat spread design.

• 반도체디스플레이기술학회지
• /
• 제22권1호
• /
• pp.124-128
• /
• 2023

반도체 양산을 진행하며 얻어지는 여러 공정 데이터들로 사용 전압을 예측하여 에너지 효율적인 제품을 위한 목적으로 연구를 시작했다. 각각의 feature들 단독으로 전압을 예측하기 어려웠던 문제를 머신 러닝을 통해, 특히 Ensemble model을 이용함으로써 단일 모델보다 정확한 예측을 할 수 있었다. 더욱 중요한 시사점으로는 feature importance 분석을 통해 모델 예측에 영향이 큰 feature와 작은 feature에 대한 분석이다. 영향도가 높은 feature를 통해 비슷한 계열의 측정값을 늘리고, 낮은 feature 들의 문제점을 개선함으로써 차세대 제품에서 더욱 정확도 높은 모델을 위한 발판을 마련할 수 있었다.

• 대한전자공학회논문지
• /
• 제27권5호
• /
• pp.699-708
• /
• 1990

This paper proposes two test procedures for detecting functional faults in semiconductor random access memories (RAM's) and a new testimg scheme to execute the proposed test procedures. The first test procedure detects stuck-at faults, coupling faults and decoder faults, and requires 19N operations, which is an improvement over conventional procedures. The second detects restricted patternsensitive faults and requires 69N operations. The proposed scheme uses Built-In Self Testing (BIST) techniques. The scheme can write into more memory cells than I/O pins can in a write cycle in test mode. By using the scheme, the number of write operations is reduced and then much testing time is saved.

• 대한산업공학회지
• /
• 제29권2호
• /
• pp.179-189
• /
• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.