• 제목/요약/키워드: Semiconductor Packaging

검색결과 280건 처리시간 0.02초

탄화규소(SiC) 반도체를 사용한 모듈에서의 방열 거동 해석 연구 (Comparative Study on the Characteristics of Heat Dissipation using Silicon Carbide (SiC) Powder Semiconductor Module)

  • 정청하;서원;김구성
    • 마이크로전자및패키징학회지
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    • 제25권4호
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    • pp.89-93
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    • 2018
  • 1200V 이상 급의 전기자동차의 파워 모듈에 적용되는 세라믹 기판은 구동 전력으로 고전력이 인가되는 특성상 고열전도도, 고 전기절연성, 저열팽창계수, 급격한 온도 변화에 대한 저항성의 특성이 요구된다. 방열기판에 적용되는 세라믹 중 질화알루미늄과 질화규소는 그 요구를 충족하는 소재로서 고려되고 있다. 이에 따라 본 논문에서는 질화알루미늄과 질화규소의 방열기판 소재로서의 특성을 상용해석프로그램을 통해 비교하였다. 그 결과 질화규소는 질화알루미늄에 대해 각각 동일한 조건의 열을 부여하는 공정을 시물레이션으로 구현했을 때 스트레스와 휨이 덜 발생하여 더 우세한 내충격성, 내stress성을 보였다. 열전도도 측면에서는 질화알루미늄이 방열 소재로서 더 우수한 특성을 지니지만 신뢰성 측면에서는 질화규소가 더 우세함을 시물레이션을 통해 관찰하였다.

Packaging MEMS, The Great Challenge of the $21^{st}$ Century

  • Bauer, Charles-E.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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    • pp.29-33
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    • 2000
  • MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than $9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

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Hands-On Experience-Based Comprehensive Curriculum for Microelectronics Manufacturing Engineering Education

  • Ha, Taemin;Hong, Sang Jeen
    • Transactions on Electrical and Electronic Materials
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    • 제17권5호
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    • pp.280-288
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    • 2016
  • Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

결정성 SiO2 충진 EMC(Epoxy Molding Compounds)봉지재의 성형조건 및 물성에 관한 연구 (Studies on Molding Conditions and Physical Properties of EMC(Epoxy Molding Compounds) fiiled with Crystalline SiO2 for Microelectronic Encapsulation)

  • 김원호;배종우;강호영;이무정;최일동
    • 공업화학
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    • 제8권3호
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    • pp.533-542
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    • 1997
  • 회로 설계의 고속화, 고성능화 경향으로 인해 반도체 봉지제의 유전특성은 회로실행과 신뢰성에 지대한 영향을 미친다. 또한 칩이 고집적화됨에 따라 신뢰성에 영향을 주는 방열성이 주요 인자가 되고 있다 결과적으로 선진적인 반도체 봉지재 제조에 있어 4가지 주요한 특성은 낮은 유전상수값, 높은 열전도도, 상대적으로 낮은 열팽창계수, 낮은 제조원가 등이다. 본 연구에서는 에폭시 봉지제의 고성능화를 위해 에폭시 모제의 충진제로서 결정성 실리카를 사용하였다 그 결과 실리카 부피량 60~70%일 때, 보다 뛰어난 물성을 갖는 반도체 봉지재를 제조할 수 있음을 확인하였다. 또한 이 실험 과정에서 반도체 봉지제의 성형조건도 설정할 수 있었다.

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반도체 패키징용 금-코팅된 은 와이어의 부식특성 (Corrosion Characteristics of Gold-Coated Silver Wire for Semiconductor Packaging)

  • 홍원식;김미송;김상엽;전성민;문정탁;김영식
    • Corrosion Science and Technology
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    • 제20권5호
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    • pp.289-294
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    • 2021
  • In this study, after measuring polarization characteristics of 97.3 wt% Ag, Au-Coated 97.3 wt% Ag (ACA) and 100 wt% Au wires in 1 wt% H2SO4 and 1 wt% HCl electrolytes at 25 ℃, corrosion rate and corrosion characteristics were comparatively analyzed. Comparing corrosion potential (ECORR) values in sulfuric acid solution, ACA wire had more than six times higher ECORR value than Au wire. Thus, it seems possible to use a broad applied voltage range of bonding wire for semiconductor packaging which ACA wire could be substituted for the Au wire. However, since the ECORR value of ACA wire was three times lower than that of the Au wire in a hydrochloric acid solution, it was judged that the use range of the applied voltage and current of the bonding wire should be considered. In hydrochloric acid solution, 97.3 wt% Ag wire showed the highest corrosion rate, while ACA and Au showed similar corrosion rates. Additionally, in the case of sulfuric acid solution, all three types showed lower corrosion rates than those under the hydrochloric acid solution environment. The corrosion rate was higher in the order of 97.3 wt% Ag > ACA > 100 wt% Au wires.

반도체 패키징용 기계식 프레스의 최적설계에 관한 연구 (A Study on the Optimal Design of Mechanical Molding Press for Semiconductor Packaging)

  • 김문기
    • 한국생산제조학회지
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    • 제22권3호
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    • pp.356-363
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    • 2013
  • Mechanical molding press which is used for transformation process during semiconductor manufacturing process has structural deformations by pressure. If these deformations have over limit range, life of the press itself can be reduced and it will be exerted on a bad effect for quality of the semiconductor. In this research, the main plates and links of a press are analyzed in relation to the structural deformations caused by pressure excluding thermal deformations. After modifying the modeling, the analysis is performed again to determine optimal design of the press, and this design is introduced to ensure that most of the stresses on the main plates are within safe allowable limits. As a result, an optimal design method for the structure is investigated to produce the desired pressure even when the size of the main structure is minimized.

CSP의 Multi-sorting을 위한 pick and place 시스템의 개발 (The development of Pick and place system for multi-sorting of CSP)

  • 김찬용;곽철훈;이은상
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.171-174
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    • 1997
  • The great development of semiconductor industry demands the high efficiency and performance of related device, but the pick and place system of semiconductor packaging device can load a few units until nowdays. Although the system can load a lot of units, it can work multiple sort operation. The defect like that causes a low efficiency. Therefore, this paper represents the development of pick and place system which can work multiple sort operation.

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Pb-free Status and Strategy of Semiconductor Business in Samsung Electronics

  • Jeong Se-Young
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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    • pp.79-92
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    • 2004
  • RoHS compliant products are now being mass-produced. Eco-product(Pb-free+RoHS compliant+Halogen-free) will be possible from 2005. Pb-free flip chip will be qualified by 2004. 4Q. Lead Finish: SnBi-Under mass production Pd PPF-Under small production Matte Sn-will be internally qualified by 2004. 4Q Development of Pb-free Solder Ball: Stable Supply, Cost Down.

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High-density Through-Hole Interconnection in a Silicon Substrate

  • Sadakata, Nobuyuki
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 International Symposium
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    • pp.165-172
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    • 2003
  • Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

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