• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.39-43
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• 2010

According to recent changes in industry for the semiconductor device, a gap between patterns in wafer is getting narrow. And this narrow gap makes a failure of uniform deposition between center and edge on the wafer. In this paper, for solving this problem, we analyze and manipulate the gas flow inside of the HDP CVD chamber by using CFD(Computational Fluid Dynamics). This simulation includes design manipulations in heights of the chamber and shape of center nozzle in the upper side of the chamber. The result of simulation shows 1.28 uniformity which is lower 3% than original uniformity.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.32-37
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• 2019

In this paper, we have designed a solar photovoltaic system to attach solar photovoltaic modules to each module and develop the best efficiency in each module. The efficiency of the designed solar panel optimizer was more than 99.27% and MPPT efficiency of 99.66%. In addition, the monitoring of power generation and abnormal operation phenomenon in each optimum period and tracking for failure location of specific photovoltaic module have improved the utilization rate of photovoltaic power generation. Wired and wireless communication methods has been proposed to monitor the power generation and operation status of the solar panel optimizer. For this purpose, the RS485 communication was used for wire communication and Zigbee communication was used for wireless communication to monitor the status of each module in real time. It is shown that communication redundancy can be achieved through the proposed method, and the possibility of commercialization is suggested.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.1-7
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• 2023

Recently, in the semiconductor industry, memory device market is focusing on producing ultra-thin wafers for high integration. In the wafer manufacturing process, wafers after backgrinding and CMP process must be picked up as individual dies and subjected to be peeled off from the dicing tape. However, ultra-thin dies are vulnerable to the possibility of breakage and failure in their thickness and size. This research studies the mechanism of peeling a die with a high-aspect ratio using a thermopneumatic method instead of a die ejector with physical pins. Setting compressed air and the temperature as main factors, we determine the success of the digester using thermopneumatic system and analyze the good die to find the possibility of making mass-production equipment.

• Journal of IKEEE
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• v.20 no.3
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• pp.251-259
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• 2016

This paper describes that how to enhance the robustness of semiconductor TRM(Transmitter and Receiver Module) through the bias sequencing and tuning the switching time. Previous circuit designs focused on improving the MDS(Minimum Detection Signal) performance. Because TRM has critical problem which transmission output signal leak into receiver by it's compact design. Under this condition, TRM was frequently broken down within the MTBF(Mean Time Between Failure). This study proposes the bias sequencing and tuning the switching time to improve above problem. At first, we collected major failure symptom and infer it's cause. Second, we demonstrated it's effect by derive the improvement method and apply it to our system. And finally we can convinced that the proposed method clear the frequent failure problem with its lack of isolation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.401-402
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• 2008

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2000.04a
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• pp.235-238
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• 2000

This article presents an adaptive decision tree algorithm for dynamically reasoning machine failure cause out of real-time, large-scale machine status database. On the basis of experiment using semiconductor etching machine, it has been verified that our model outperforms previously proposed decision tree models.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.598-606
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• 2001

Recently, semiconductor packages trend to be thinner, which makes difficult to detect defects therein. A preconditioning test is generally performed to evaluate the reliability of semiconductor packages. The test procedure includes two scanning acoustic microscope (SAM) tests at the beginning and end of the entire test, in order to help detect physical defects such as delaminations and package cracks. In particular, of primary concern are package cracks and delaminations caused by moisture absorbed under ambient conditions. This paper discusses the failure mechanism associated with the moisture absorbed and encapsulated in semiconductors, and the use SAM to detect failures such as tracks and delaminations grown during the preconditioning test.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.