• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.657-658
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• 2013

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.401-406
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• 1988

Various types and huge volume of information such as process instructions, work-in process and parametric data are created in a wafer fabrication process and should be provided to personnels inside or outside the facility. This article describes design criteria and functional description on the information system for small-scale wafer fabrication process to accomplish paperless fab and to support efficient fab management.

• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.236-244
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• 2014

Presented in the paper is a reservation based dispatching rule to achieve the on-time delivery in system LSI (large scale integrated circuit) semiconductor fabrication (FAB) with urgent orders. Using the proposed reservation based dispatching rule, urgent lots can be processed without waiting in a queue. It is possible to achieve the on-time delivery of urgent orders by reserving a proper tool for the next step in advance while urgent lots are being processed at the previous step. It can cause, however, tardiness of normal lots, because the proposed rule assign urgent lots first. To solve this problem, the proposed rule tries to find the best tool for the reservation in the tool group, which can minimize idle time, and the reservation rule is applied at all tools except for photolithography tools (bottleneck). $MOZART^{(R)}$ which is developed by VMS solutions are used for simulation experiments. The experimentation results show that the reservation based dispatching rule can achieve the on-time delivery of normal lots as well as urgent lots.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.1765-1770
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• 2006

본 논문에서는 반도체 fab 라인의 물류 설비를 event graph로 모델링 하는 방법론을 제안하고 있다. 최근 반도체 fab 라인 같은 대표적인 자본 집약적 제조라인에서는 운영단계에서 투입 계획, PM schedule 및 operation rule 등을 변화시켜 가며 평가 및 검증해 볼 수 있는 what-if simulation을 위한 line simulator의 필요성이 점점 높아지고 있다. 그러나 상용 simulator는 각 제조라인의 특성에 맞게 customization하는데 많은 시간과 비용이 소요될 뿐만 아니라 특성을 반영하는데 한계가 있다. 따라서 이러한 line simulator를 개발할 때 근간이 되는 설비의 simulation model이 필요하다. 이 때 설비들은 생산(processing) 및 물류(handling) 설비로 나눌 수 있는데, 본 논문에서는 반도체 fab 라인의 물류 설비 모델링 방법을 제시하고 실제 물류 설비를 모델링 해 봄으로써 그 효용성을 알아본다.

• Journal of Intelligence and Information Systems
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• v.9 no.1
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• pp.157-177
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• 2003

This paper presents a comprehensive and successful application of data mining methodologies to improve and predict wafer yield in a semiconductor wafer fabrication system. As the wafer fabrication process is getting more complex and the volume of technological data gathered continues to be vast, it is difficult to analyze the cause of yield deterioration effectively by means of statistical or heuristic approaches. To begin with this paper applies a clustering method to automatically identify AUF (Area Uniform Failure) phenomenon from data instead of naked eye that bad chips occurs in a specific area of wafer. Next, sequential pattern analysis and classification methods are applied to and out machines and parameters that are cause of low yield, respectively. Furthermore, radial bases function method is used to predict yield of wafers that are in process. Finally, this paper demonstrates an information system, Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis & Up Support), that is developed in order to analyze and predict wafer yield in a korea semiconductor manufacturer.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.59-65
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• 2002

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. Project executed that use conveyor in bay semiconductor A line. But conveyor capability is lacking and rundown happened in equipment. Do design without normal simulation and conveyor system failed. The comparison is peformed through simulation using .AutoMod a window 98 based discrete system simulation software, as a tool for comparing performance of proposed layouts. In this research estimate optimum conveyor capability, there is the purpose.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.1074-1081
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• 2009

The importance of improving semiconductor fab layout has been increased with the necessity of a large-scale capital investment and the increase of manufacturing complexity of the system. For the present, most semiconductor fab takes the form of a bay type layout where the same types of machines has been laid at the same bay. The bay type layout has many disadvantages in respect of material flow control even though it has merits of flexibility. To overcome the drawbacks of the bay type layout, a new room type semiconductor layout which integrates bays without a center spine and maintains the flexibilities of the bay type has been presented and compared with existing layouts. The results of test show that the room type layout is superior to the existing layouts from standpoints of transportation number and time, foot-print, number of stocker being passed and material flow time.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.275-286
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• 2015

In this paper, we propose a practical method for setting up a daily production plan which can operate semiconductor fabrication factories more stably and linearly by determining work in process (WIP) targets and movement targets. We first adjust cycle times of the operations to satisfy the monthly production plan. Second, work in process (WIP) targets are determined to control the production progress of operations: earliness and tardiness. Third, movement targets are determined to reduce cumulated differences between WIP targets and actual WIPs. Finally, the determined movement targets are modified through a simulation model which considers capacities of the equipments and allocations of the WIPs in the fab. The proposed daily production planning method can be easily adapted to the memory semiconductor fabs because the method is very simple and has straightforward logics. Although the proposed method is simple and straightforward, the power of the method is very strong. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed daily production planning method will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.

• Journal of the Korea Society for Simulation
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• v.28 no.4
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• pp.11-20
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• 2019

This paper presents a HILS(Hardware-In-the-Loop Simulation) approach for the verification of the OHT (Overhead Hoist Transport) controller in a semiconductor FAB. Since hundreds of OHTs can run simultaneously on the OHT network of a FAB, the full verification of the OHT controller is very essential to guarantee the stableness of the material handling system. The controller needs to fully consider not only normal situations but also abnormal situations that are difficult to predict. For the verification of the controller, we propose a HILS approach using a virtual environment including OHTs on a rail network, which can generate abnormal situations. The proposed HILS approach has been implemented and tested with various examples.