• Journal of the Korea Society for Simulation
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• v.12 no.3
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• Journal of Applied Reliability
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• v.16 no.1
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• Journal of Powder Materials
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• v.8 no.4
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• pp.245-252
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• 2001

Recent remarkable progress in the semiconductor industry has promoted smaller size of semiconductor chips and increased amounts of heat generation. So, the demand for a substrate material to meet both the characteristics of thermal expansion coefficient and heat radiation has been on the increase. Under such conditions, tungsten(W)-copper(Cu) has been proposed as materials to meet both of the above characteristics. In the present study, the W-10wt.%Cu powders were synthesised by the mixing and hydrogen reduction of the starting mixture materials such as W-Cu, $W-CuCl_2$and $WO_3-CuCl_2$ in order to obtain the full densification. The W-10wt.%Cu produced by hydrogen reduction showed the higher interparticle friction than the simple mixed W-10wt%Cu because of the W agglomerates. In the dilatometric analysis the W-10wt.%Cu prepared from the $W-CuCl_2$was largely shrank by heating up $1400^{\circ}C$ at the constant heating rate of $5^{\circ}C$/min. The possibility of application of metal injection molding (MIM) was also investigated for mass production of the complex shaped W-Cu parts in semiconductor devices. The relationship between the temperature of molding die and the pressure of injection molding was analyzed and the heating up stage of 120-$290^{\circ}C$ in the debinding process was controlled for the most suitable MIM condition.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.2
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.949-958
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• 2018

A voice recognition control system is a system for controlling a peripheral device by recognizing a voice. Recently, a voice recognition control system have been applied not only to smart devices but also to various environments ranging from IoT(: Internet of Things), robots, and vehicles. In such a voice recognition control system, the recognition rate is lowered due to the ambient noise in addition to the voice of the user. In this paper, we propose a dual channel acoustic beamforming hardware architecture for MEMS(: Microelectromechanical Systems) microphones to eliminate ambient noise in addition to user's voice. And the proposed hardware architecture is designed as ASIC(: Application-Specific Integrated Circuit) using TowerJazz $0.18{\mu}m$ CMOS(: Complementary Metal-Oxide Semiconductor) technology. The designed dual channel acoustic beamforming ASIC has a die size of $48mm^2$, and the directivity index of the user's voice were measured to be 4.233㏈.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.19-25
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• 2023

With an attempt to investigate the correlation between the internal pressure distribution of slit nozzle and the thickness uniformity of slot-coated thin films, we have performed computational fluid dynamics (CFD) simulations of slit nozzles and slot coating of high-viscosity (4,800 cPs) polydimethylsiloxane (PDMS) using a gantry slot-die coater. We have calculated the coefficient of variation (CV) to quantify the pressure and velocity distributions inside the slit nozzle and the thickness non-uniformity of slot-coated PDMS films. The pressure distribution inside the cavity and the velocity distribution at the outlet are analyzed by varying the shim thickness and flow rate. We have shown that the cavity pressure uniformity and film thickness uniformity are enhanced by reducing the shim thickness. It is addressed that the CV value of the cavity pressure that can ensure the thickness non-uniformity of less than 5% is equal to and less than 1%, which is achievable with the shim thickness of 150 ㎛. It is also found that as the flow rate increases, the average cavity pressure is increased with the CV value of the pressure unchanged and the maximum coating speed is increased. As the shim thickness is reduced, however, the maximum coating speed and flow rate decrease. The highly uniform PDMS films shows the tensile strain as high as 180%, which can be used as a stretchable substrate.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.28-35
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• 2023

Moiré patterns emerge due to the interference between the non-emission area of the LED screen and the grid line in an image sensor of a video recording device when taking a video in the presence of the LED screen. To reduce the moiré intensity, we have fabricated an anti-moiré filter using hollow glass microspheres (HGMs) by slot-die coating. The LED screen has a large non-emission area because of a large pitch (distance between LED chips), causing more severe moiré phenomenon, compared with a display panel having a very narrow black matrix (BM). It is shown that HGMs diffuse light in such a way that the periodicity of the screen is broken and thus the moiré intensity weakens. To quantitatively analyze its moiré suppression capability, we have calculated the spatial frequencies of the moiré fringes using fast Fourier transform. It is addressed that the moiré phenomenon is suppressed and thus the amplitude of each discrete spatial frequency term is reduced as the HGM concentration is increased. Using the filter with the HGM concentration of 9 wt%, the moiré fringes appeared depending sensitively on the distance between the LED screen and the camera are almost completely removed and the visibility of a nature image is enhanced at a sacrifice of luminance.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.2004-2006
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• 1996

A thermally driven polysilicon micro actuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS (tetracthylorthosilicate) as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE (vapor phase etching) process was also used as an effective release method for the elimination of sacrificial TEOS layer. The thickneas of polysilicon is $2{\mu}m$ and the lengths of active and passive polysilicon cantilevers are $500{\mu}m$ and $260{\mu}m$, respectively. The actuation is incurred by die thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon micro actuator was experimentally conformed as large as $21{\mu}m$ at the input voltage level of 10V and 50Hz square wave. The actuating characteristics are investigated by simulating the phenomena of heat transfer and thermal expansion in the polysilicon layer. The displacement of actuator is analyzed to be proportional to the square of input voltage. These micro actuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as micro relay, which requires large displacement or contact force but relatively slow response.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.845-848
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• 2009

Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronics circuits. Theyare also caleed power devices or when used in integrated circuits, called power ICs. Some common power devices are the power diode, thyristor, power MOSFET and IGBT (insulated gate bipolar transistor). A power diode or MOSFET operates on similar principles to its low-power counterpart, but is able to carry a larger amount of current and typically is able to support a larger reverse-bias voltage in the off-state. Structural changes are often made in power devices to accommodate the higher current density, higher power dissipation and/or higher reverse breakdown voltage. The vast majority of the discrete (i.e non integrated) power devices are built using a vertical structure, whereas small-signal devices employ a lateral structure. With the vertical structure, the current rating of the device is proportional to its area, and the voltage blocking capability is achieved in the height of the die. With this structure, one of the connections of the device is located on the bottom of the semiconductor.