• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.6-10
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• 2019

In the presence of $\mu-tip$ for narrow stripe coating, there appears lateral capillary flow along the hydrophilic head lip because the $\mu-tip$ has some resistance to flow. It was known to be suppressed by increasing the contact angle of the head lip. In this paper, we have demonstrated by computational fluid dynamics(CFD) simulations that it can also be suppressed by the formation of micro-patterns on the shim and meniscus guide embedded into the slot-die head. To optimize the micro-patterned structure, we have performed simulations by varying the groove width, depth, and clearance. In the absence of micro-patterns, it is shown by experiment and simulation that the solution spreads to a distance of $1,300{\mu}m$ from the ${\mu}-tip$. In the presence of micro-patterns with the groove width and clearance of $50{\mu}m$, the distance the solution spreads is reduced to $260{\mu}m$. However, no further suppression in the capillary flow is observed with micro-patterns with the groove width of $40{\mu}m$ or less. It is also observed that the capillary flow is not affected by the groove depth if it is larger than $10{\mu}m$. We have shown that the distance the solution spreads can be reduced further to $204{\mu}m$ by coating a hydrophobic material (contact angle of $104^{\circ}$) on the surface of micro-patterns having the groove width and clearance of $50{\mu}m$.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.92-96
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• 2019

In the presence of ${\mu}-tip$ embedded in a slot-die head for stripe coatings, there arises the capillary flow that limits an increase of the stripe density, which is required for the potential applications in organic light-emitting diode displays. With an attempt to suppress it, we have employed a computational fluid dynamics software and performed simulations by varying the ${\mu}-tip$ length and the contact angles of the head lip and ${\mu}-tip$. We have first demonstrated that such a capillary flow phenomenon (a spread of solution along the head lip) observed experimentally can be reproduced by the computational fluid dynamics software. Through simulations, we have found that stronger capillary flow is observed in the hydrophilic head lip with a smaller contact angle and it is suppressed effectively as the contact angle increases. When the contact angle of the head lip increases from $16^{\circ}$ to $130^{\circ}$, the distance a solution can reach decreases sharply from $256{\mu}m$ to $44{\mu}m$. With increasing contact angle of the ${\mu}-tip$, however, the solution flow along the ${\mu}-tip$ is disturbed and thus the capillary flow phenomenon becomes more severe. If the ${\mu}-tip$ is long, the capillary flow also appears strong due to an increase of flow resistance (electronic-hydraulic analogy). It can be suppressed by reducing the ${\mu}-tip$ length, but not as effectively as reducing the contact angle of the head lip.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.33-38
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• 2022

With an attempt to suppress the moiré phenomenon caused by the interference between the black matrix of a display panel and the metal grid of a camera, we have fabricated an anti-moiré filter using light diffusing particles (LDPs) with the average diameter of 20 ㎛. It is demonstrated that the anti-moiré filter coated on a glass substrate (370 mm × 470 mm) using a table slot-die coater reduces the moiré intensity to a great extent when the area covered by LDPs is 50%. To quantify the intensity of moiré phenomenon, we have measured the lightness ratio and found that it is reduced from 132.12 down to 105.71 by the filter. To find the optimum area covered by LDPs, we have performed ray tracing simulations using Mie scatters as a substitute for LDPs. From the simulated irradiation distribution, we have calculated the standard deviation (SD) and contrast ratio (CR) to evaluate the moiré strength. As expected, the SD and CR values decrease with increasing covered area by LDPs. However, there exists a trade-off between the transmittance of the filter and its capability of reducing the moiré intensity in determining the area covered by LDPs.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.129-135
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• 2019

4M D램 공동연구 개발사업(1986.10~89.03)은 당시 미 일의 강력한 기술보호주의를 극복하기 위한 자구책으로 시작되었다. 국내 반도체업계는 선진국의 높은 기술장벽 및 기술보호주의를 극복하고, 강력한 경쟁력확보 및 기술축적을 위해 정부에 건의하였다. 이에 정부는 적극적인 자금지원을 통해 4M D램 개발 및 주변기술 개발을 목표로 초고집적반도체기술공동개발사업을 수행하게 되었다. 본 공동R&D사업은 ETRI의 주관으로 당시 금성반도체, 삼성전자, 현대전자산업 등의 반도체 업체와 학계가 참여하였고, 1986년 10월부터 1989년 3월까지 3단계에 걸쳐 수행되었다. 공동연구의 목적은 설계, 공정, 조립, 검사 등 4M D램 제조와 관련되는 기본기술개발과 함께 $0.8{\mu}m$ 선폭의 4M D램을 개발하는 것이며, 이를 위해 단계별 목표를 설정하고 관민연의 혼연일치로 추진되었다. 1차년에는 중요 핵심기술개발, 2차년에는 $0.8{\mu}m$ 4M D램 Working-die개발, 3차년에는 수율 20%의 $0.8{\mu}m$ 4M D램 양산시 제품을 목표대로 완료하였다. 각 연구단계별로 주요 핵심기술에 대한 연구평가가 실시되었으며, 관련기술에 대한 중복투자 방지를 위해 2차년도부터 분담연구가 수행되었고, 상호 기술공유를 위한 기술교류회가 활발히 이루어졌다. 또한 R&D수행을 통해 4M D램 Working-die를 2차년도 중반에 개발완료하였으며, 3차년도에는 4M D램의 20% 수율확보와 공정기술의 최적화 및 DB 구축을 수행했다. 공동R&D 방식에서도 기업간 경쟁체제 도입에 입각하여 동기유발 형태로 진행되었다. 정부는 자금적 지원으로 기업간의 경쟁 심리를 자극하는 전략을 추진했다. 선두기업인 삼성에게는 선행적 개발 지위에 비례하여 더 많은 지원을 부여하는 대신에, 삼성의 기술성과를 다른 기업에게로 확산시킴으로써 반도체 3사 전체의 기술능력을 향상시키는 전략을 추진했다. 본 사업이 성공적으로 수행되어 반도체 제품의 세계시장 점유율제고, 국제수지 개선, 반도체 핵심기술 조기확보뿐만 아니라 16M D램급 이상 차세대 반도체기술 개발의 교도보가 되었다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.9
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• pp.1-11
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• 2022

Recently, there has been continuous technological development in the semiconductor industry, and semiconductor manufacturing technologies are being advanced and highly integrated. For this reason, ceramic material having excellent heat resistance, wear resistance, and conductivity are used as components in semiconductor manufacturing. Among them, the probe card's space transformer is used as ceramic material to prevent electronic signal noise during the electrical die sorting of semiconductor function testing. However, implementing a bulk-type space transformer with a thickness of 5.6 mm or more is challenging, and thus it is produced in a structure with a stacked ceramic film. The stacked space transformer has low productivity because it is difficult to ensure hole clogging and a precise shape. In this research, an ultrasonic horn is designed to manufacture a bulk-type ceramic space transformer through ultrasonic drilling. Vibration characteristics were analyzed according to the ultrasonic horn, and the natural frequency was measured.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.