• Title/Summary/Keyword: Semiconductor Defect

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The development of Pick and place system for multi-sorting of CSP (CSP의 Multi-sorting을 위한 pick and place 시스템의 개발)

  • 김찬용;곽철훈;이은상
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.10a
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    • pp.171-174
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    • 1997
  • The great development of semiconductor industry demands the high efficiency and performance of related device, but the pick and place system of semiconductor packaging device can load a few units until nowdays. Although the system can load a lot of units, it can work multiple sort operation. The defect like that causes a low efficiency. Therefore, this paper represents the development of pick and place system which can work multiple sort operation.

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Detected Point Clustering Algorithm For Automatic Visual Inspection (자동외관검사를 위한 검출위치 클러스터링 알고리즘)

  • Ryu, Sun Joong
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.3
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    • pp.1-6
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    • 2014
  • Visual defect inspection for electronics parts manufacturing processes is comprised of 2 steps - automatic visual inspection by machine and inspection by human inspectors. It is necessary that spatial points which were detected by the machine should be adequately clustered for subsequent human inspection. This research deals with the spatial clustering algorithm for the purpose of process productivity improvement. Distribution based clustering is newly developed and experimentally confirmed to show better clustering efficiency than existing algorithm - area based clustering.

Studies on Flip Chip Underfill Process by using Molding System (몰딩공정을 응용한 플립칩 언더필 연구)

  • 한세진;정철화;차재원;서화일;김광선
    • Journal of the Semiconductor & Display Technology
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    • v.1 no.1
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    • pp.29-33
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    • 2002
  • In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

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Thermal Diffusion Process Modeling with Adaptive Finite Volume Method (적응성 유한체적법을 적용한 다차원 확산공정 모델링)

  • 이준하;이흥주
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.3
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    • pp.19-21
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    • 2004
  • This paper presents a 3-dimensional diffusion simulation with adaptive solution strategy. The developed diffusion simulator VLSIDIF-3 was designed to re-refine areas. Refine scheme was calculated by the difference of doping concentration between any of two nodes. Each element is greater than tolerance and redo diffusion process until error is tolerable. Numerical experiment in low doping diffusion problem showed that this adaptive solution strategy is very efficient in both memory and time, and expected this scheme would be more powerful in complex diffusion model.

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Defect Characterization & Control for the Metal Contact with CVD Barrier Metal in Memory Device (반도체 제품의 CVD Barrier Metal기인 Contact불량 연구)

  • Park, Sang-Jun;Yoon, Joo-Byoung;Lee, Kyung-Woo;Lee, Sang-Ick;Kim, Jin-Sung;Chae, Seung-Ki;Chae, Hee-Sun;Roh, Yong-Han
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.179-180
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    • 2007
  • 반도체의 최소 회로 선폭이 감소함에 따라 Contact 저항이 크게 증가하게 된다. Contact 저항을 낮추기 위하여 Tungsten Metal Contact을 일반적으로 사용하며, Si 기판과의 Ohmic 접촉 및 WF6의 Fluorine과 Si 반응을 억제하기 위한 Barrier Metal로 Ti/TiN 이중막을 사용한다. 본 논문에서는 90nm급 이하 제품의 CVD Ti/TiN Barrier Metal이 유발하는 불량 현상과 원인 규명에 대하여 연구하였으며, Ohmic Contact형성을 위해 TiSix형성 최적화 방안에 대해 정리하였다.

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The Development of Pattern Classification for Inner Defects in Semiconductor Packages by Self-Organizing Map (자기조직화 지도를 이용한 반도체 패키지 내부결함의 패턴분류 알고리즘 개발)

  • 김재열;윤성운;김훈조;김창현;양동조;송경석
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.12 no.2
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    • pp.65-70
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    • 2003
  • In this study, researchers developed the estimative algorithm for artificial defect in semiconductor packages and performed it by pattern recognition technology. For this purpose, the estimative algorithm was included that researchers made software with MATLAB. The software consists of some procedures including ultrasonic image acquisition, equalization filtering, Self-Organizing Map and Backpropagation Neural Network. Self-organizing Map and Backpropagation Neural Network are belong to methods of Neural Networks. And the pattern recognition technology has applied to classify three kinds of detective patterns in semiconductor packages : Crack, Delamination and Normal. According to the results, we were confirmed that estimative algerian was provided the recognition rates of 75.7% (for Crack) and 83.4% (for Delamination) and 87.2 % (for Normal).

A Study on the Defect Detection of Silicon-Chip Surrounding by Ultrasonic Wave - Automatic Determination Method of Threshold Value by Image Processing - (초음파를 이용할 실리콘 칩 주위의 결함 검출에 관한 연구 - 화상처리에 의한 threshold value의 자동 결정법 -)

  • 김재열;박환규
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1991.11a
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    • pp.87-94
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    • 1991
  • This Paper is to aim the microdefect evaluation of semiconductor Package into a quantitative from NDI's image processing of ultrasonic wave. Accordingly, for the detection of delamination between the Joining condition of boundary microdefect of semiconductor packaga the result from sampling original image, histogramming, binary image or image processing of multinumerloal value is such as the follows. ([) The least limitation from the microdefect detection of the semiconductor package by surveying high ultrasonic wave seems to be about 0.8 $\mu\textrm{m}$ in degree. (2) A result of applying the image processing of multinumerical value to the semiconductor package it was possible to devide the Category into the effectiveness.

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Non-Destructive Evaluation of Semiconductor Package by Electronic Speckle Pattern Interferometry

  • Kim, Koung-Suk;Kang, Ki-Soo;Jung, Seung-Tack
    • Journal of Mechanical Science and Technology
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    • v.19 no.3
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    • pp.820-825
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    • 2005
  • This paper proposes non-destructive ESPI technique to evaluate inside defects of semiconductor package quantitatively. Inspection system consists of ESPI system, thermal loading system and adiabatic chamber. The technique has high feasibility in non-destructive testing of semiconductor and gives solutions to the drawbacks in previous technique, time-consuming and the difficulty of quantitative evaluation. In result, most of defects are classified in delamination, from which it is inferred to the insufficiency of adhesive strength between layers and nonhomogeneous heat spread. The $90\%$ of tested samples have a delamination defect started at the around of the chip which may be related to heat spread design.

A method and analysis of human-error management of a semiconductor industry (반도체산업에서의 인적오류제어방법 및 연구)

  • Yoon Yong-Gu;Park Peom
    • Journal of the Korea Safety Management & Science
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    • v.8 no.1
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    • pp.17-26
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    • 2006
  • Basis frame-work's base in a semiconductor industry have gas, chemical, electricity and various facilities in bring to it. That it is a foundation by fire, power failure, blast, spill of toxicant huge by large size accident human and physical loss and damage because it can bring this efficient, connect with each kind mechanical, physical thing to prevent usefully need that control finding achievement factor of human factor of human action. Large size accident in a semiconductor industry to machine and human and it is involved that present, in system by safety interlock defect of machine is conclusion for error of behaviour. What is not construing in this study, do safety in a semiconductor industry to do improvement. Control human error analyzes in human control with and considers mechanical element and several elements. Also, apply achievement factor using O'conner Model by control method of human error. In analyze by failure mode effect using actuality example.

Performance Improvement of Asynchronous Mass Memory Module Using Error Correction Code (에러 보정 코드를 이용한 비동기용 대용량 메모리 모듈의 성능 향상)

  • Ahn, Jae Hyun;Yang, Oh;Yeon, Jun Sang
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.3
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    • pp.112-117
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    • 2020
  • NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.