• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.391-391
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• 2016

The carrier transport is a key factor that determines the device performances of semiconductor devices such as solar cells and transistors [1]. Particularly, devices composed of in amorphous semiconductors, the transport is often restricted by carrier trapping, associated with various defects. So far, the trapping has been studied for as-grown films at room temperature; however it has not been studied during growth under plasma processing. Here, we demonstrate the detection of trapped carriers in hydrogenated amorphous silicon (a-Si:H) films during plasma processing, and discuss the carrier trapping and defect kinetics. Using an optically pump-probe technique, we detected the trapped carriers (electrons) in an a-Si:H films during growth by a hydrogen diluted silane discharge [2]. A device-grade intrinsic a-Si:H film growing on a glass substrate was illuminated with pump and probe light. The pump induced the photocurrent, whereas the pulsed probe induced an increment in the photocurrent. The photocurrent and its increment were separately measured using a lock-in technique. Because the increment in the photocurrent originates from emission of trapped carriers, and therefore the trapped carrier density was determined from this increment under the assumption of carrier generation and recombination dynamics [2]. We found that the trapped carrier density in device grade intrinsic a-Si:H was the order of 1e17 to 1e18 cm-3. It was highly dependent on the growth conditions, particularly on the growth temperature. At 473K, the trapped carrier density was minimized. Interestingly, the detected trapped carriers were homogeneously distributed in the direction of film growth, and they were decreased once the film growth was terminated by turning off the discharge.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.3
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• pp.200-205
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• 2015

An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

• Korean Journal of Materials Research
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• v.27 no.1
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• pp.48-52
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• 2017

In this study, we used I-V spectroscopy, photoconductivity (PC) yield and internal photoemission (IPE) yield using IPE spectroscopy to characterize the Schottky barrier heights (SBH) at insulator-semiconductor interfaces of Pt/$HfO_2$/p-type Si metal-insulator-semiconductor (MIS) capacitors. The leakage current characteristics of the MIS capacitor were analyzed according to the J-V and C-V curves. The leakage current behavior of the capacitors, which depends on the applied electric field, can be described using the Poole-Frenkel (P-F) emission, trap assisted tunneling (TAT), and direct tunneling (DT) models. The leakage current transport mechanism is controlled by the trap level energy depth of $HfO_2$. In order to further study the SBH and the electronic tunneling mechanism, the internal photoemission (IPE) yield was measured and analyzed. We obtained the SBH values of the Pt/$HfO_2$/p-type Si for use in Fowler plots in the square and cubic root IPE yield spectra curves. At the Pt/$HfO_2$/p-type Si interface, the SBH difference, which depends on the electrical potential, is related to (1) the work function (WF) difference and between the Pt and p-type Si and (2) the sub-gap defect state features (density and energy) in the given dielectric.

• Journal of Adhesion and Interface
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• v.25 no.2
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• pp.63-68
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• 2024

In this study, the contamination of gold(Au) wire according to the types of rinse applied for surface treatment in the wire bonding process is investigated and confirmed. For the surface treatment, rinses containing silicon(Si) or those based on organic materials are mainly employed. To identify their effects, surface treatment is conducted on Au wire using two types of rinse at a 1.0 wt% concentration, referred to as Si-including and Oil-based rinse-coated Au wire. Subsequently, a simulation experiment is performed to verify the reactivity of dust containing Si components that could occur in the semiconductor process. Through optical microscopy (OM) and scanning electron microscopy(SEM) analysis, it is observed that a larger amount of dust is adsorbed on the surface of Si-including rinse-coated Au wire compared with the Oil-based rinse-coated Au wire. This is attributed that the rinse containing Si components is relatively polar, causing polar interactions with dust, which also has polarity. Therefore, it is expected that using a rinse without Si components can reduce contamination caused by dust, thereby decreasing the defect rate in the practical wire bonding process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.226-235
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• 2016

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

• Journal of the Korean Ceramic Society
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• v.28 no.6
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• pp.495-501
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• 1991

This study is intended to make defect-free region, denuded zone at the silicon wafer surface for semiconductor device substrates. In this experiment, initial oxygen concentration of starting material CZ-grown silicon wafer, various heat treatment combinations, denuding ambient and the amounts of oxygen reduction were measured, and then denuded zone (DZ) formation and depth were investigated. In Low/High anneal (DZ formation could be achieved), the optimum temperature for Low anneal was 700$^{\circ}C$∼750$^{\circ}C$. In case of High anneal, with the time increased, DZ depth was increased at 1000$^{\circ}C$, 1150$^{\circ}C$ respectively, but on the contrary, DZ depth was decreased at low temperature 900$^{\circ}C$. As well, out-diffusion time below 2 hours was unsuitable for effective Gettering technique even though the temperature was high, and DZ formation could be achieved when initial oxygen concentration was only above 14 ppm in silicon wafer.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.04a
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• pp.466-471
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• 2004

In focused-ion-beam (FIB) application of micromachining and device transplantation, four kinds of FIB processes, namely FIB sputtering, FIB-induced etching, redeposition, and FIB-induced deposition, are well utilized. As with FIB systems, scanning electron microscopes(SEMs) were extensively used in the semiconductor industry. They are the tools of choice for defect review and providing the image resolution needed for process monitoring. The enhanced capabilities of a dual-column on one chamber system are quickly becoming realized by the nano industry for performing a wide range of application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.32 no.3
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• pp.99-109
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• 2009

Negative binomial yield model for semiconductor manufacturing consists of two parameters which are the average number of defects per die and the clustering parameter. Estimating the clustering parameter is quite complex because the parameter has not clear closed form. In this paper, a Bayesian approach using Markov Chain Monte Carlo is proposed to estimate the clustering parameter. To find an appropriate estimation method for the clustering parameter, two typical estimators, the method of moments estimator and the maximum likelihood estimator, and the proposed Bayesian estimator are compared with respect to the mean absolute deviation between the real yield and the estimated yield. Experimental results show that both the proposed Bayesian estimator and the maximum likelihood estimator have excellent performance and the choice of method depends on the purpose of use.