• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.26-31
• /
• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• Journal of the Korea Convergence Society
• /
• v.10 no.11
• /
• pp.85-93
• /
• 2019

Despite its matchless position in the global semiconductor industry, Korea has not distinguished itself in the semiconductor equipment sector. Semiconductor cleaning equipment is one of the semiconductor fabrication equipment, and it is expected to be more important along with the advancement of semiconductor fabrication processes. This study attempts to analyze technology competitiveness of major countries in the sector including Korea, and explore specialty sub-areas of the countries. For this purpose, we collected patents of semiconductor cleaning equipment during the last 10 years from the US patent database, and implemented quantitative patent analysis and co-classification network analysis. The result shows that, the US and Japan have been leading the technological progress in this sector, and Korea's competitiveness has lagged behind not only the leading countries but also its competitors and even latecomers. Therefore, intensive R&D and developing technological capabilities are needed for advancing the country's competitiveness in the sector.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.4
• /
• pp.73-78
• /
• 2016

Contact pressure distribution between PVA brush and semiconductor wafer was measured by developing a test setup which could simulates the post CMP cleaning process. The test set-up used thin film type pressure sensor which could measure the pressure distribution of contact area with the resolution of $15.5ea/cm^2$. As the experimental results, it was verified that there had been severe contact pressure non-uniformity along the axis of the brush and between the adjacent projections on the brush's surface. These results should be considered when developing post CMP cleaning stage or designing the PVA brush.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.3 no.2
• /
• pp.74-79
• /
• 2002

In the a rapid changes of the semiconductor manufacturing technologies for early 21st century, it may be safely said that a kernel of terms is the size increase of Si wafer and the size decrease of semiconductor devices. As the size of Si wafers increases and semiconductor device is miniaturized, the units of cleaning processes increases. A present cleaning technology is based upon RCA cleaning which consumes vast chemicals and ultra pure water (UPW) and is the high temperature process. Therefore, this technology gives rise to the environmental issue. To resolve this matter, candidates of advanced cleaning processes has been studied. One of them is to apply the electrolyzed water. In this work, Compared with surface on Si wafer with electrolyzed water cleaning and various chemicals cleaning, and analyzed Si wafer surface condition treated with elecoolyzed water by cleaning temperature and cleaning time. Especially. concentrate upon the contact angle. finally, contact angle on surface treated with cathode water cleaning is 17.28, and anode water cleaning is 34.1.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.66-71
• /
• 2023

This paper describes a hybrid cleaning method of silicon wafer combining nano-bubble and ultrasound to remove sub-micron particles and contaminants with minimal damage to the wafer surface. In the megasonic cleaning process of semiconductor manufacturing, the cavitation induced by ultrasound can oscillate and collapse violently often with re-entrant jet formation leading to surface damage. The smaller size of cavitation bubbles leads to more stable oscillations with more thermal and viscous damping, thus to less erosive surface cleaning. In this study, ultrasonic energy was applied to the wafer surface in the DI water to excite nano-bubbles at resonance to remove contaminant particles from the surface. A patented nano-bubble generator was developed for the generation of nano-bubbles with concentration of 1×10⁹ bubbles/ml and nominal nano-bubble diameter of 150 nm. Ultrasonic nano-bubble technology improved a contaminant removal efficiency more than 97% for artificial nano-sized particles of alumina and Latex with significant reduction in cleaning time without damage to the wafer surface.

• Journal of the Korean Society of Visualization
• /
• v.9 no.1
• /
• pp.17-19
• /
• 2011

The bubble oscillations play an important role in ultrasonic cleaning processes. In the ultrasonic cleaning of semiconductor wafers, the cleaning process often damages micro/nano scale patterns while removing contaminant particles. However, the understanding of how patterns in semiconductor wafers are damaged during ultrasonic cleaning is far from complete yet. Here, we report the observations of the motion of bubbles that induce solid wall damage under 26 kHz continuous ultrasonic waves. We classified the motions into the four types, i.e. volume motion, shape motion, splitting or jetting motion and chaotic motion. Our experimental results show that bubble oscillations get unstable and nonlinear as the ultrasonic amplitude increases, which may exert a large stress on a solid surface raising the possibility of damaging microstructures.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.2
• /
• pp.45-50
• /
• 2020

We investigated the Si_1-xGe_x surface properties when dry cleaning the films using NF₃ / H₂O remote plasma. After the dry cleaning process, it was found that about 80-250 nm wide bumps were formed on the SiGe surface regardless of Ge concentration in the rage of x = 0.1 ~ 0.3. In addition, effects of the dry cleaning processing parameters such as pressure, substrate temperature, and H₂O flow rates were examined. It was found that the surface bump is significantly dependent on the flow rate of H₂O. Based on these observations, we would like to provide additional guidelines for implementing the dry cleaning process to SiGe materials.

• Clean Technology
• /
• v.5 no.1
• /
• pp.62-77
• /
• 1999

Semiconductor industry has rapidly grown because of the need from electronic and computer industries. However the global environmental regulations for various hazardous chemical compounds, which are indispensably used in semiconductor manufacturing process, are getting stronger. The semiconductor industries should develop the cleaner technologies in order to both lead the future world market and avoid the regulations form environmentally developed countries. In this paper, cleaner technologies for semiconductor cleaning processes are surveyed, such as gas phase process, UV process, and plasma process. Advantages and disadvantages of these processes are discussed.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.99-104
• /
• 1993

We analyzed the D.I. water used in wet cleaning process of semiconductor device manufacturing both at the D.I. water plant and at the wafer cleaning bath to detect the impurity source of D.I. water contamination. This shows that the quantity of impurity is related to the resistivity of D.I. water, and we found that the cleanliness of the wafer surface processed in D.I. water bath was affected by the degree of the ionic impurity contamination. So we evaluated the cleaning effect as different method for Fe ion, having the best adsoptivity on wafer surface. Moreover the temperature effect of the D.I. water is investigated in case of anion in order to remove the chemical residue after wet process. In addition to the control of D.I. water resistivity, chemical analysis of impurity control in D.I. water should be included and a suitable cleaning an drinsing method needs to be investigated for a high yielding semiconductor device.

• Proceedings of the KSME Conference
• /
• 2007.05b
• /
• pp.3168-3172
• /
• 2007

As the minimum feature size decreases, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT and designed a particle deposition system which consists of scanning mobility particle sizer (SMPS) and deposition chamber. Charged monodisperse particles are generated using SMPS and deposited on the wafer by electrostatic force. The experimental results agreed with the simulation results well in terms of particle number and deposition area according to particle size, flow rate and deposition voltage.