• Journal of the Semiconductor & Display Technology
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• v.23 no.3
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• pp.96-101
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• 2024

In this study, we report on the joining of mullite ceramics using the reaction-bonded aluminum oxide method without applying any external pressure, in consideration of a possible multilayer ceramic substrate in semiconductor back-end process. For this purpose, Al/Al2O3/SiO2/Mullite powder mixture paste was applied to the joining surfaces between two parent mullite bodies of the same composition, and then sintered at 1,650 ℃ for 2 h in air, resulting in a dense and rigid mullite ceramic joints. Phase and microstructural analysis of the joined mullites showed that the reaction bonding by Al oxidation and thereafter mullite formation were completed during the heat treatment process. However, due to the difference in sintering behavior between the parent body and the joining layer, few pore of which size proportional to the joining layer thickness, were observed at some parts of the joining interface. The formation of the pore and its causes was discussed.

• International Area Studies Review
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• v.20 no.2
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• pp.85-111
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• 2016

Global semiconductor companies is investing enormous capital worldwide. And direct investment in China is increasing greatly these days, Especially, global semiconductor companies are setting up a factory in China due to expanding market rather than utilizing low labor cost. Therefore, this study is trying to analyze the background and process of direct investment from global Korean and Taiwanese semiconductor companies in China. Firstly, In 1996, Samsung semiconductor established a back end process factory in Suzhou. And in 2014, Samsung semiconductor set up a front and back end factory in Xian. Secondly, In 2006, SK Hynix built a front and back end factory in Wuxi. and SK Hynix set up a back end factory named Hitech semiconductor with Chinese company in 2009. Later in 2015, SK Hynix established a back end factory in Chongqing. Thirdly, In 2004, TSMC started to operate a factory in Shanghai, and in 2018, TSMC is going to establish a factory in Nanjing. Lastly, UMC bought a stock to produce product in Chinese local company named HJT, and at the end of 2016, UMC is going to finish building a factory in Xiamen. As a result, it was proved that most companies hoped to expand the chinese market by setting up a factory in china. In addition, Samsung expected to avoid a risk by setting up a factory in china, and SK Hynix wanted to avoid a countervailing duty by setting up a factory in china. Based on the result of this study, this study indicates some implications for other semiconductor companies which are very helpful for their future foreign direct investment.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2002.11a
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• pp.65-67
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• 2002

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.107-113
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• 2003

Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.107-113
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• 2024

Scheduling of semiconductor test facilities has been crucial since effective scheduling contributes to the profits of semiconductor enterprises and enhances the quality of semiconductor products. This study aims to solve the scheduling problems for the wafer burn-in test facilities of the semiconductor back-end process by utilizing simulation and deep reinforcement learning-based methods. To solve the scheduling problem considered in this study. we propose novel state, action, and reward designs based on the Markov decision process. Furthermore, a neural network is trained by employing the recent RL-based method, named proximal policy optimization. Experimental results showed that the proposed method outperformed traditional heuristic-based scheduling techniques, achieving a higher due date compliance rate of jobs in terms of total job completion time.

• Journal of IKEEE
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• v.28 no.2
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• pp.158-167
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• 2024

In this study, U-net model based on electrical capacitance is applied to monitor the condition inside the pipeline of semiconductor rear end process implemented in the numerical simulation. Capacitance values measured from electrodes attached to the pipeline is used as input data for the U-net network model and estimated permittivity distribution by the U-net model is used to reconstructed cross-sectional image at the pipeline. In the numerical simulation, images reconstructed by U-net model, Fully-connected neural network (FCNN) model and Newton-Raphson method are compared for evaluation. U-net model shows good results as compared to other models.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• Transactions on Electrical and Electronic Materials
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• v.12 no.4
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• pp.131-134
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• 2011

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.