Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Residual deposit monitoring of semiconductor back-end process using U-net model based on the electrical capacitance

전기 정전용량을 기반으로 U-net 모델을 이용한 반도체 후단 공정의 잔류물 모니터링

  • Minho JEON (Dept. of Electronics Engineering, Jeju National University) ;
  • Anil Kumar Khambampati (Dept. of Electronics Engineering, Jeju National University) ;
  • Kyung-Youn Kim (Dept. of Electronics Engineering, Jeju National University)
  • 전민호 ;
  • 아닐쿠마 ;
  • 김경연
  • Received : 2024.05.13
  • Accepted : 2024.06.19
  • Published : 2024.06.30
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Abstract

In this study, U-net model based on electrical capacitance is applied to monitor the condition inside the pipeline of semiconductor rear end process implemented in the numerical simulation. Capacitance values measured from electrodes attached to the pipeline is used as input data for the U-net network model and estimated permittivity distribution by the U-net model is used to reconstructed cross-sectional image at the pipeline. In the numerical simulation, images reconstructed by U-net model, Fully-connected neural network (FCNN) model and Newton-Raphson method are compared for evaluation. U-net model shows good results as compared to other models.

본 논문에서는, 시뮬레이션 상에서 반도체 후단 공정의 프로세스를 구현하고 파이프 내부 상황을 모니터링하기 위해 전기 정전용량을 기반으로 한 U-net 모델을 적용하였다. 배관에 부착된 전극에서 측정한 정전용량 값은 U-net 네트워크 모델의 입력 데이터로 사용되며, 모델을 통해 추정한 유전율 분포를 가지고 파이프 단면을 이미지화하였다. 성능 평가를 위해 수치 시뮬레이션 얀에서 U-net 모델, FCNN(Fully-connected neural network) 모델, Newton-Raphson 방법으로 재구성한 이미지를 비교한 결과, U-net이 다른 이미지 복원 방식보다 좋은 복원 성능을 보였다.

Keywords

Acknowledgement

This research was supported by the 2023 scientific promotion program funded by Jeju National University

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