• 반도체디스플레이기술학회지
• /
• 제23권3호
• /
• pp.96-101
• /
• 2024

In this study, we report on the joining of mullite ceramics using the reaction-bonded aluminum oxide method without applying any external pressure, in consideration of a possible multilayer ceramic substrate in semiconductor back-end process. For this purpose, Al/Al2O3/SiO2/Mullite powder mixture paste was applied to the joining surfaces between two parent mullite bodies of the same composition, and then sintered at 1,650 ℃ for 2 h in air, resulting in a dense and rigid mullite ceramic joints. Phase and microstructural analysis of the joined mullites showed that the reaction bonding by Al oxidation and thereafter mullite formation were completed during the heat treatment process. However, due to the difference in sintering behavior between the parent body and the joining layer, few pore of which size proportional to the joining layer thickness, were observed at some parts of the joining interface. The formation of the pore and its causes was discussed.

• 국제지역연구
• /
• 제20권2호
• /
• pp.85-111
• /
• 2016

최근, 글로벌 반도체기업들의 중국내 직접투자가 지속적으로 증가하고 있다. 특히, 중국내에서 제조를 위한 공장설립이 늘고 있으며, 이는 저렴한 인건비를 활용하기 위한 차원보다는 늘어나는 중국내 수요에 대응하려 투자하고 있다. 이에 따라 본 연구에서는 한국과 대만 글로벌 반도체기업들에 대한 중국내 직접투자 배경과 과정에 대해서 살펴보았다. 조사결과 삼성반도체는 1996년 Suzhou에 후 공정 공장을 설립하였으나 전 공정의 일괄생산방식으로 투자한 것은 2014년 Xian공장이었다. 그리고 SK하이닉스는 2006년 Wuxi에 처음 공장을 설립하였으며 이후 2009년 중국기업과 합작으로 후 공정 공장인 Hitech Semiconductor를 설립하였고 이어 2015년 Chongqing에 후 공정 공장을 설립하였다. 아울러 TSMC는 2004년 Shanghai에서 처음 공장을 가동하였으며 나아가 2018년에 Nanjing공장이 완공예정이다. 마지막으로 UMC는 2000년대 초반 중국 현지기업인 HJT에 지분을 소유하는 방식으로 중국에 진출하였으며, 이후 직접투자로 빠르면 2016년 말 Xiamen공장이 완공된다. 결과적으로 각사 대부분은 주로 중국시장을 공략하기 위한 목적으로 중국에 공장설립을 한 것으로 나타났으나 이외에도 삼성반도체는 리스크 관리 그리고 SK하이닉스는 상계관세를 회피하기 위한 목적이 있었다. 본 연구결과를 토대로 다른 반도체기업들에 차후 중국내 직접투자에 있어 도움이 되는 전략적 시사점들을 제시하였다.

• 한국레이저가공학회:학술대회논문집
• /
• 한국레이저가공학회 2002년도 추계학술발표대회 논문개요집
• /
• pp.65-67
• /
• 2002

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권3호
• /
• pp.107-113
• /
• 2003

Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.

• 반도체디스플레이기술학회지
• /
• 제23권2호
• /
• pp.107-113
• /
• 2024

Scheduling of semiconductor test facilities has been crucial since effective scheduling contributes to the profits of semiconductor enterprises and enhances the quality of semiconductor products. This study aims to solve the scheduling problems for the wafer burn-in test facilities of the semiconductor back-end process by utilizing simulation and deep reinforcement learning-based methods. To solve the scheduling problem considered in this study. we propose novel state, action, and reward designs based on the Markov decision process. Furthermore, a neural network is trained by employing the recent RL-based method, named proximal policy optimization. Experimental results showed that the proposed method outperformed traditional heuristic-based scheduling techniques, achieving a higher due date compliance rate of jobs in terms of total job completion time.

• 전기전자학회논문지
• /
• 제28권2호
• /
• pp.158-167
• /
• 2024

본 논문에서는, 시뮬레이션 상에서 반도체 후단 공정의 프로세스를 구현하고 파이프 내부 상황을 모니터링하기 위해 전기 정전용량을 기반으로 한 U-net 모델을 적용하였다. 배관에 부착된 전극에서 측정한 정전용량 값은 U-net 네트워크 모델의 입력 데이터로 사용되며, 모델을 통해 추정한 유전율 분포를 가지고 파이프 단면을 이미지화하였다. 성능 평가를 위해 수치 시뮬레이션 얀에서 U-net 모델, FCNN(Fully-connected neural network) 모델, Newton-Raphson 방법으로 재구성한 이미지를 비교한 결과, U-net이 다른 이미지 복원 방식보다 좋은 복원 성능을 보였다.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2001년도 춘계학술대회 논문집
• /
• pp.1117-1120
• /
• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• 전자공학회논문지D
• /
• 제34D권12호
• /
• pp.76-82
• /
• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• Transactions on Electrical and Electronic Materials
• /
• 제12권4호
• /
• pp.131-134
• /
• 2011

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.93-94
• /
• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.