• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1419-1421
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• 1995

Nickel micro-structures are fabricated by electroless plating which shows better uniformity. Positive resist AZ4562 of 7 um thickness is patterned with minimum width of 2 um on poly-silicon as for sacrificial layer. The growth rate of Ni electroless plating is 10um/h both for the seed layer of Pt and TiW. TiW is found to be more practical than Pt, since it is very difficult to remove Pt with negligible damage to Ni structures.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.2-291.2
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• 2016

3D semiconductor material of silicon that is used throughout the semiconductor industry currently faces a physical limitation of the development of semiconductor process technology. The research into the next generation of nano-semiconductor materials such as semiconductor properties superior to replace silicon in order to overcome the physical limitations, such as the 2-dimensional graphene material in 2D transition-metal dichalcogenide (TMD) has been researched. In particular, 2D TMD doping without severely damage of crystal structure is required different conventional methods such as ion implantation in 3D semiconductor device. Here, we study a p-type doping technique on tungsten diselenide (WSe2) for p-channel 2D transistors by adjusting the concentration of hydrochloric acid through Raman spectroscopy and electrical/optical measurements. Where the performance parameters of WSe2 - based electronic device can be properly designed or optimized. (on currents increasing and threshold voltage positive shift.) We expect that our p-doping method will make it possible to successfully integrate future layered semiconductor devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.172-173
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• 2002

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1270-1272
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• 2007

Analytic equations are derived from physical quantities in the gate-source overlap region and the concept of effective gate-source overlap length is proposed. The effective overlap length can be affected by gate voltage, insulator thickness and semiconductor thickness, and the overlap length should be larger than the length to obtain maximum driving current.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.270-271
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• 2008

The contact resistance between organic semiconductor and source-drain electrode in Bottom Contact Organic Thin-Film Transistors (BCOTFTs) can be effectively reduced by metal oxide/molybdenum double layer structure; metal oxide layers including nickel oxide (NiOx/Mo) and moly oxide(MoOx) under molybdenum work as a high performance carrier injection layer. Step profiles of source-drain electrode can be easily achieved by simultaneous etching of the double layers using the difference etching rate between metal oxides and metal layers.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.481-482
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• 2008

In this paper, the advanced process has been presented to remove the WSix peeling that was made in sub 100nm DRAM SRCAT(Sphere-shaped-Recess-Ch annel-Array Transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (Chemical Mechanical Polishing) process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.668-675
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• 2013

We investigate the effect of the ageing time and etching time on the etching rate of SiGe mixed etching solution, namely 1 vp HF (6%), 2 vp $H_2O_2$ (30%) and 3 vp $CH_3COOH$ (99.8%). For this etching solution, we found that the etch rate of SiGe layer is saturated after the ageing time of 72 hours, and the selectivity of $Si_{0.8}Ge_{0.2}$ layer and Si layer is 20:1 at ageing time of 72 hours. The collapse was appeared at the etching time of 9min with etching solution of after saturation ageing time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.67-74
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• 1994

Effects of the GaAs semiconductor particles on electrophysical phenomena at the Pt electrode/10S0-3TM KCl aqueous electrolyte interfaces have been studied using voltammetric time based and electrochemical impedance techniques. The anodic decomposition effect f the GaAs semiconductor particles on electrophysical phenomena was significantly observed during the positive potential scan (0 to 1.0 V vs. SCE). On the other hand, the cathodic decomposition effect of the GaAs semiconductor particles was negligible during thenegative potential scan (0 to -1.0 V vs. SCE). The GaAs semiconductor particles act as current activators or mediators during the anodic process and act as charge screens during the cathodic process. The electrolyte resistance and related impedance was increased due to the presence of the GaAs semiconductor particles. The anodic decomposition effect of the GaAs semiconductor particles can directly be applied to activate the hydrogen evolution.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.