• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.450-455
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• 2010

The performance modeling of a $25{\mu}m$ pitch VGA ${\mu}$-bolometer with the self-aligned thermal resistor structure is carried out. The self-aligned thermal resistor can be utilized for the maximizing the thermal resistance and the fill factor of a bolometer, so the performance improvement can be expected. From the results of the performance modeling of the micro-bolometer with self-align thermal resistor for a $25{\mu}m$ pitch $640{\times}480$ microbolometer designed with $0.6{\mu}m$ minimum feature size, the drastic improvements of NETD from 38.7 mK to 19.1 mK, responsivity of 1.9 times are expected with a self aligned thermal resistor structure. The main reason for the performance improvements with a self-aligned thermal resistor structure comes from the increasement of the thermal resistance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.367-372
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• 2006

A carbon nanotube field emission display(CNT FED) panel with a 2 inch diagonal size was fabricated using a screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After a surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20 nm. Using the photo-sensitive CNT paste, we have developed a triode type CNT FEA with a self-aligned gate-emitter structure. The turn on voltage was around 100 V which corresponds to according the turn on field of about $40V/{\mu}m$. By the creation of a self-aligned gate-emitter structure, it is expected that the screen printed photo-sensitive CNT paste is promising as a good candidate for the large size field emission display.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.88-93
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• 1998

For the self-aligned AlGaAs/GaAs HBTs, the surface states at the interface between the extrinsic base surface and the passivation nitride is a major cause of degradation of dc characteristics. In this paper the degradation mechanisms of self-aligned AlGaAs/GaAs HBT were analyzed, and GaAs HBTs, which employed an InGaP ledge emitter structure formed by the nonself-aligned process to cover the surface of the extrinsic base and reduce the surface states, produced high reliability. Accoridng to the acceleration lifetime test, the nonself-aligned InGaP/GaAs HBTs produced very reliable dc characteristics comparing with the self-aligned AlGaAs/GaAs HBTs. The activation energy was 1.97eV and MTTF $4.8{\times}10^{8}$ hrs at $140^{\circ}C$ which satisfied the MIL standard.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.1-5
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• 2000

A waveguide of coupled optical modulator was fabricated on LiNbO$_3$ based on proton exchange with self-aligned thin film electrode method. The electrode pattern was designed using a self-aligned method. After proton exchange process, the waveguide was prepared by annealing process. The initial crossover state of the fabricated 2$\times$2 coupled optical modulator was observed with controlling the annealing process variables and the structure of self-aligned thin film electrodes. It was shown form the present work that the measured crosstalk is -29.5[dB] and 8.0[V] of detected modulating voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.6
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• pp.448-453
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• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.7
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.536-540
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• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).