• 제목/요약/키워드: Selective Harmonics Elimination Method

검색결과 13건 처리시간 0.023초

Elimination of Low Order Harmonics in Multilevel Inverters Using Genetic Algorithm

  • Salehi, Reza;Farokhnia, Naeem;Abedi, Mehrdad;Fathi, Seyed Hamid
    • Journal of Power Electronics
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    • 제11권2호
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    • pp.132-139
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    • 2011
  • The selective harmonic elimination pulse width modulation (SHEPWM) switching strategy has been applied to multilevel inverters to remove low harmonics. Naturally, the related equations do not have feasible solutions for some operating points associated with the modulation index (M). However, with these infeasible points, minimizing instead of eliminating harmonics is performed. Thus, harmful harmonics such as the $5^{th}$ harmonic still remains in the output waveform. Therefore, it is proposed in this paper to ignore solving the equation associated with the highest order harmonics. A reduction in the eliminated harmonics results in an increase in the degrees of freedom. As a result, the lower order harmonics are eliminated in more operating points. A 9-level inverter is chosen as a case study. The genetic algorithm (GA) for optimization purposes is used. Simulation results verify the proposed method.

Reconfigurable Selective Harmonic Elimination Technique for Wide Range Operations in Asymmetric Cascaded Multilevel Inverter

  • Kavitha, R;Rani, Thottungal
    • Journal of Power Electronics
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    • 제18권4호
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    • pp.1037-1050
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    • 2018
  • This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

Harmonic Elimination in Three-Phase Voltage Source Inverters by Particle Swarm Optimization

  • Azab, Mohamed
    • Journal of Electrical Engineering and Technology
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    • 제6권3호
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    • pp.334-341
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    • 2011
  • This paper presents accurate solutions for nonlinear transcendental equations of the selective harmonic elimination technique used in three-phase PWM inverters feeding the induction motor by particle swarm optimization (PSO). With the proposed approach, the required switching angles are computed efficiently to eliminate low order harmonics up to the $23^{rd}$ from the inverter voltage waveform, whereas the magnitude of the fundamental component is controlled to the desired value. A set of solutions and the evaluation of the proposed method are presented. The obtained results prove that the algorithm converges to a precise solution after several iterations. The salient contribution of the paper is the application of the particle swarm algorithm to attenuate successfully any undesired loworder harmonics from the inverter output voltage. The current paper demonstrates that the PSO is a promising approach to control the operation of a three-phase voltage source inverter with a selective harmonic elimination strategy to be applied in induction motor drives.

A Practical Algorithm for Selective Harmonic Elimination in Five-Level Converters

  • Golshan, Farzad;Abrishamifar, Adib;Arasteh, Mohammad
    • Journal of Power Electronics
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    • 제18권6호
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    • pp.1650-1658
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    • 2018
  • Multilevel converters are being widely used in medium-voltage high-power applications including motor drive systems, utility power transmission, and distribution systems. Selective harmonic elimination (SHE) is a well-known modulation method to generate high quality output voltage waveforms. This paper presents a new simple practical method for generating a generalized five-level waveform without selected low order harmonics. This method is based on a phase-shifted expression for the SHE problem, which can analytically calculate the exact values of switching angles and the feasible modulation index range for three-level and five-level waveforms. The proposed method automatically determines the number of transitions between levels and generates proper output waveform without solving complex trigonometric equations. Due to the simplicity of the computational burden, the real-time implementation of the proposed algorithm can be performed by a simple processor. Simulation and experiment results verify the correctness and effectiveness of the proposed method.

Grid-friendly Control Strategy with Dual Primary-Side Series-Connected Winding Transformers

  • Shang, Jing;Nian, Xiaohong;Chen, Tao;Ma, Zhenyu
    • Journal of Power Electronics
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    • 제16권3호
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    • pp.960-969
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    • 2016
  • High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

Increasing the Range of Modulation Indices with the Polarities of Cells and Switching Constraint Reliefs for the Selective Harmonic Elimination Pulse Width Modulation Technique

  • Najjar, Mohammad;Iman-Eini, Hossein;Moeini, Amirhossein
    • Journal of Power Electronics
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    • 제17권4호
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    • pp.933-941
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    • 2017
  • In this paper an improved low frequency selective harmonic elimination-PWM (SHE-PWM) technique for Cascaded H-bridge (CHB) converters is proposed. The proposed method is able to eliminate low order harmonics from the output voltage of the converter for a wide range of modulation indices. To solve SHE-PWM equations, especially for low modulation indices, a modified method is used which employs either the positive or negative voltage polarities of H-bridge cells to increase the freedom degrees of each cell. Freedom degrees of the switching angles are also used to increase the range of available solutions for non-linear SHE equations. The proposed SHE methods can successfully eliminate up to $25^{th}$ harmonic from a 7-level output voltage by using just nine switching transitions or a 150 Hz switching frequency. To confirm the validity of the proposed method, simulation and experimental results have been presented.

Walsh-Fourier 변환을 사용한 PWM 인버어터의 고조파 제거 방법 (A Harmonic Elimination Method of PWM Inverter Using Walsh-Fourier Transform)

  • 안두수;원충연;이해기;김태훈;김학성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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    • pp.296-300
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    • 1989
  • The paper proposes a method to eliminate harmonics of PWM inverter fed induction motor system using Walsh series. In other words, this paper presents technique of the selective harmonics elimination(SHE) by W-FT series in three phase PWM inverter output waveform. A microprocessor(8086 CPU) - controlled three phase induction motor system in order to verify this algorithm is present. It is designed for a three output voltage in the 1$\sim$60 Hz inverter with the 5th and 7th harmonics, 5th, 7th, 11th, and 13th, harmonics eliminated, and with the fundamental wave amplitude proportional to the output frequency. In the PWM inverter, dead time circuit is inserted in the switching si gnats to prevent the de link shortage. This paper is deals with quantative prediction of dead-time effect and its compensation in PWM inverters. The performance of the compensation circuits is confirmed by the experiment.

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Natural Balancing of the Neutral Point Potential of a Three-Level Inverter with Improved Firefly Algorithm

  • Gnanasundari, M.;Rajaram, M.;Balaraman, Sujatha
    • Journal of Power Electronics
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    • 제16권4호
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    • pp.1306-1315
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    • 2016
  • Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

FACTS 적용을 위한 직렬형 멀티레벨 전압형 인버터를 사용한 1MVar STATCON의 새로운 스위칭기법 (Novel Switching Strategy of 1MVar STATCON using Cascade Multilevel Voltage Source Inverter for FACTS Application)

  • 민완기;민준기;최재호
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제48권12호
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    • pp.691-700
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    • 1999
  • This paper proposes a novel switching strategy of 1Mvar STATCON using cascade multilevel H-bridge inverter(HBI) for FACTS application. To control the reactive power instantaneously, the d-q dynamic system model is described and analyzed. A single pulse pattern based on the SHEM(Selective Harmonic Elimination Method) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is presented to adjust the DC voltage of each inverter capacitor at the same value. So the voltage unbalance problem between separately DC bus voltage is improved by using the proposed switching scheme. As a result, the presented inverter configuration not only reduces the system complexity by eliminating the isolation at the AC input side transformer but also improves the dynamic response to the step change of reactive power.

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A New Switching Pattern for Multilevel Inverter Based on Selective Harmonic Elimination Using Genetic Algorithm

  • Fekari, Seyyed Amir;Iranaq, Ali Reza Marami;Sabahi, Mehran
    • Journal of international Conference on Electrical Machines and Systems
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    • 제3권3호
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    • pp.305-311
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    • 2014
  • In this paper, a new switching pattern is presented for multilevel inverters. With changing off-angel of each switch, the on time interval of all switches will approximately be equal and then the lifetime of inverter will increase, also using this method can reduce electrical stress on switches in higher levels of inverter. Switching angels as for desired modulation index are calculated using genetic algorithm whereas selective harmonics are controlled within the allowable range. The computed angels are simulated in Matlab/Simulink for respective circuits to validate the results.