• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.451-454
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• 2006

본 논문에서는 헬기의 인공 시계 시스템용 DGPS/INS 통합 항법 플랫폼을 설계하였다. DGPS/INS 통합 항법 플랫폼 하드웨어는 PowerPC CPU와 Flash ROM과 DDR SDRAM를 이용하여 설계하였다. DGPS 수신기와 IMU와의 연결을 위한 외부 인터페이스부는 직렬 통신을 사용하는 DGPS수신기와 IMU는 모두 사용할 수 있도록 하기 위하여 직렬 통신 방식인 UART 컨트롤러와 SDLC 컨트롤러를 사용하여 설계하였다. 실시간 운영체제를 기반으로 하는 플랫폼의 소프트웨어는 초기 정렬, 자세 계산, 속도 계산, 위치 계산, 통합 필터, 명령 처리 각각에 대하여 태스크로 구성하고 세마포어를 이용하여 태스크간의 동기가 이루어지도록 설계하였다. 통합 항법 플랫폼의 성능 평가를 위하여 차량 실험을 수행하였으며 상용 항법 시스템의 결과와 비교를 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.3-5
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• 2000

1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.443-452
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• 2004

The paper presents an intelligent space management system for ubiquitous computing. The system is basically a home/office automation system that could control light, electronic key, and home appliances such as TV and audio. On top of these basic capabilities, there are four elegant features in the system. First, we can access the system using either a cellular Phone or using a browser on the PC connected to the Internet, so that we control the system at any time and any place. Second, to provide more human-oriented interface, we integrate voice recognition functionalities into the system. Third, the system supports not only reactive services but also proactive services, based on the regularities of user behavior. Finally, by exploiting embedded technologies, the system could be run on the hardware that has less-processing power and storage. We have implemented the system on the embedded board consisting of StrongARM CPU with 205MHz, 32MB SDRAM, 16MB NOR-type flash memory, and Relay box. Under these hardware platforms, software components such as embedded Linux, HTK voice recognition tools, GoAhead Web Server, and GPIO driver are cooperated to support user-friendly intelligent space.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.4
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• pp.315-324
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• 2005

VOD(video on demand) is a video service by users' order, that is, a video service on demand. That means the users can select and watch the video content that has been saved on sewer, out of broadcasting in the usual process like TV. At present the client of VOD system bases on PC. As the PC-based client uses the software MPEG decoder, the main processor specification has an effect on the capacity. Also people, who don't know how to use their PC, cannot be provided the VOD service. The purpose of this paper is to show the process of the development the VOD client system Into the embedded type with hardware MPEG-4 decoder. The main processor is the SC1200 of x86 Family in National Semiconductor with a built-in video processor and the memory is 128Mbyte SDRAM. Also, in order that the VOD service can be provided using the Internet, the Ethernet controller is included. As the hardware MPEG-4 decoder is used in the embedded VOD client system, which is developed, it can make the low capacity of the main processor. Therefore it is able to be developed as a low-price system. The embedded VOD client system is easy for anyone to control easily with the remote control and can be played through TV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.1-6
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• 2010

We can see the motion blur phenomenon on theedge of the moving picture when it moves in the LCDs. To reduce this phenomenon, we suggested a new over-deriving method, implemented on the board XUP Virtex-2 Pro Development System by using Virtex-2 Pro XUP XC2VP30 and improved the Motion Blur. In this method, we did not use additional parts except for a SDRAM. Hardware implementation for IP and data interface were handled in software. In this paper, we used the moving bar and the moving video image as a design model. We also showed that the afterimage was reduced and the vivid moving images was displayed. through this method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1119-1128
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• 2001

본 논문에서는 이차원(2-D) 이산 웨이블릿 면환(Discrete Wavelet Transform, DWT)을 이용한 연상압축기를 FPGA 칩에서 실시간으로 동작 가능하도록 하는 효율적인 메모리 스케줄링 방법(E$^2$M$^2$)을 제안하였다. S/W적으로 위의 메모리 사상 방법을 검증한 후, 실제로 상용화된 SFRAM을 선정하여 메모리 제어기를 구현하였다. 본 논문에서는 Mallet-tree를 이용한 2-D DWT 영상압축 칩을 구현할 경우를 가정하였다. 이 알고리즘은 연산 과정에서 많은 데이터를 정장하여야 하는데, FPGA는 많은 데이터를 저장할 수 있는 메모리가 내장되어 있지 않으므로 외부 메모리를 사용하여야 한다. 외부메모리는 열(row)에 대해서만 연속(burst) 읽기, 쓰기 동작이 가능하기 때문에 Mallet-tree 알고리즘의 데이터 입출력을 그대로 적용할 경우 실시간 동작을 수행하는 DWT 압축 칩을 구현할 수 없다. 본 논문에서는 데이터 쓰기를 수행할 경우에는 메모리 셀(cell)의 수직 방향을 저장시키고 읽기를 수행할 때는 수평으로 데이터의 연속 읽기를 수행함으로써 필터가 항상 수평 방향에 위치하게 하는 방법을 제안하였다. 입방법을 C-언어로 DWT 커넬(Kernel)과 메모리의 에뮬레이터(emulator)를 구현하여 실험한 결과, Mallat-tree 이론을 그대로 적용시켰을 때와 동일한 필터링을 수행할 수 있음을 검증하였다. 또한, 상용화된 SDRAM의 메모리 제어기를 H/W로 구현하여 시뮬레이션 함으로써 본 논문에서 제안한 방법이 실제적인 하드웨어로 실시간 동작을 할 수 있음을 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.