• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.1-12
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• 2003

This paper describes a study on the abnormal behavior of the electrical characteristics of the (n)GaAs/Ti/Pt/Au Schottky contacts prepared by the two techniques of electron beam deposition and rf sputtering and after an annealing treatment. The samples were characterized by I-V and C-V measurements carried out over the temperature range of 150 - 350 K both in the as prepared state and after a 300 C, 30 min. anneal step. The variation of ideality factor with forward bias, the variation of ideality factor and barrier height with temperature and the difference between the capacitance barrier and current barrier show the presence of a thin interfacial oxide layer along with barrier height inhomogenieties at the metal/semiconductor interface. This barrier height inhomogeneity model also explains the lower barrier height for the sputtered samples to be due to the presence of low barrier height patches produced because of high plasma energy. After the annealing step the contacts prepared by electron beam have the highest typical current barrier height of 0.85 eV and capacitance barrier height of 0.86 eV whereas those prepared by sputtering (at the highest power studied) have the lowest typical current barrier height of 0.67 eV and capacitance barrier height of 0.78 eV.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.10-15
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• 2006

Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from $20{\mu}m$ to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed $550{\mu}A/um$ saturation current at $V_{GS}-V_T$ = $V_{DS}$ = 2V condition ($T_{ox}$ = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.

• Electrical & Electronic Materials
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• v.9 no.7
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• pp.708-718
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• 1996

The microstructure and electrical properties of the nonlinear ZnO varistor with A1$_{2}$ $O_{3}$ additions is investigated. The variation of nonlinear behavior with A1$_{2}$ $O_{3}$ additions is indicated from J-E and C-V measurement to be a result of the change of the interface defects density $N_{t}$ at the grain boundaries and the donor concentration $N_{d}$ in the ZnO grains. The optimum composition which has the nonlinear coefficients of -57 was observed in the sample with 0.005wt% A1$_{2}$ $O_{3}$ additions. The conduction mechanism at the pre-breakdown region is consistent with a Schottky thermal emission process obeying a relation given by $J^{\var}$exp[-(.psi.-.betha. $E^{1}$2/)kT] and the conduction process at the breakdown region follows a Fowler-Nordheim tunneling mechanism of the form $J^{\var}$exp(-.gamma./E).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.75-76
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• 2007

Poly-Si Schottky barrier Thin Film Transistor (SB-TFT) is manufactured with erbium silicided source/drain. High quality poly-Si film was obtained by crystallizing the amorphous Si film with Excimer laser annealing (ELA) method. The fabricated poly-Si SB-TFT devices showed low leakage current and large on/off current ratio. Moreover, the electrical characteristics were considerably improved by 3% $H_2/N_2$ gas annealing, which is attributed to the reduction of trap states at the grain boundaries and interface trap states at gate oxide/poly-si channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.243.2-243.2
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• 2015

We report a high-performing nanoscale NiO thin film grown by thermal oxidation of sputtered Ni film. The structural, physical, optical and electrical properties of nanoscale NiO were comprehensively investigated. A quality transparent heterojunction (NiO/ZnO) was formed by large-area applicable sputtering deposition method that has an extremely low saturation current of 0.1 nA. Considerable large rectification ratio of more than 1000 was obtained for transparent heterojunction device. Mott-Schottky analyses were applied to develop the interface of NiO and ZnO by establishing energy diagrams. Nanoscale NiO has the accepter carrier concentration of the order of 1018 cm-3. Nanoscale NiO Schottky junction device properties were comprehensively studied using room temperature impedance spectroscopy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.124-127
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• 2004

W/n-GaN Schottky diodes were irradiated with $^{60}Co\;{\gamma}-rays$ to doses up to 315Mrad. The barrier height obtained from current-voltage (I-V) measurements showed minimal change from its estimated initial value of ${\sim}0.4eV$ over this dose range, though both forward and reverse I-V characteristics show evidence of defect center introduction at doses as low as 150 Mrad. Post irradiation annealing at $500^{\circ}C$ increased the reverse leakage current, suggesting migration and complexing of defects. The W/GaN interface is stable to high dose of ${\gamma}-rays$, but Au/Ti overlayers employed for reducing contact sheet resistance suffer from adhesion problems at the highest doses.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.120-123
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• 2019

The effect of surface plasmon on ZTO thin films was investigated. The phenomenon of depletion occurring in the interface of the ZTO thin film created a potential barrier and the dielectric layer of the depletion formed a non-mass particle called plasmon. ZTO thin film represents n-type semiconductor features, and surface current by plasma has been able to obtain the effect of improving electrical efficiency as a result of high current at positive voltage and low current at negative voltage. It can be seen that the reduction of electric charge due to recombination of electronic hole pairs by heat treatment of compound semiconductors induces higher surface current in semiconductor devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.671-674
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• 2009

We design a low-power and low-area asynchronous EEPROM of 256 bits used in a passive UHF RFID tag chip. For a low-power solution, we use a supply voltage of 1.8V and design a Dickson charge pump using N-type Schottky diodes with a low-voltage characteristic. And we use an asynchronous interface and a separate I/O method for a low-area solution of the peripheral circuit of the designed EEPROM. And we design a Dickson charge pump using N-type Schottky diodes to reduce an area of DC-DC converter. The layout area of the designed EEPROM of 256 bits with an array of 16 rows and 16 columns using $0.18{\mu}m$ EEPROM process is $311.66{\times}490.59{\mu}m^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.