• The Journal of the Korea Contents Association
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• v.4 no.2
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• pp.50-60
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• 2004

Recently, most of the embedded system is required not only many functions but also real-time characteristics in purpose. In the hard real-time system, especially, strict deadline of periodic task can affect the performance of the system. In this paper, we design and implement the scheduler based on RM(Rate-Monotonic) rule. This scheduler makes feasible patterns based on EDF(Earliest deadline first) rule with extended schedulability inspection before execution, for periodic task-set that has high CPU utilization and then, execute periodic task-set depended on feasible patterns. The feasible pattern formed into EDF rule is capable of the efficiency of CPU up to 100 percentage and by the referenced execution of the feasible pattern is possible of removing the red-time scheduling overhead that is the defect of the order of dynamic assignment rule.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.6
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• pp.36-46
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• 2002

This paper proposes an integrated scheduling mechanism for embedded system with real-time web server to meet the characteristics of real time task. The proposed scheduling mechanism may solve the so-called priority inversion problem in scheduling between urgent web requests and tasks with low priorities. The priority inversion problem happens because of operating two independent schedulers, web scheduler and operating system scheduler in a system without considering the requirements of each other. In the proposed mechanism, two schedulers are integrated in an operating system and the integrated scheduler schedules tasks for urgent web requests with real time characteristics and other application tasks together. Since all tasks are scheduled by one unified scheduler that knows the characteristics of tasks, the tasks are scheduled with their absolute priorities and thus the priority inversion problem can be eliminated. The performance is measured on a prototype embedded system with the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.9-16
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• 2003

In this paper, we propose an ATM processor suitable for VoDSL subscriber's equipments. The processor is composed of ATM block, AAL protocol block and ATS scheduler, and provides up to 4 VCC which service data and voice traffics on the ATM network. The proposed ATS scheduler can guarantee QoS of the voice traffic and supports multiple AAL2 packet. The ATM processor is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor and provides the maximum data transfer rate of up to 52 Mbps. We implement the LAD, which is the VoDSL subscriber's equipment. The experimental results on the test bed network shows that the proposed hardware scheme successfully services most of the applications of the VoDSL services.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.940-948
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• 2011

In this paper, we design and implement a task scheduler that considers real-time and fault tolerance in embedded system with a single processor. We propose a method how it can meet the deadlines of periodic tasks using RMS and complete the execution of aperiodic tasks by calculating surplus times from a periodic task set. And we describe a method how to recover of a transient fault task by managing backup time. We propose an important level of periodic tasks that can control the response time of periodic and aperiodic tasks. Finally, we analyse and evaluate the proposed methods by simulation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.4
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• pp.1302-1320
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• 2015

In cloud, everything can be provided as a service wherein a large number of users submit their jobs and wait for their services. hus, scheduling plays major role for providing the resources efficiently to the submitted jobs. The brainwave of the proposed ork is to improve user satisfaction, to balance the load efficiently and to bolster the resource utilization. Hence, this paper roposes an Adaptive Multilevel Scheduling System (AMSS) which will process the jobs in a multileveled fashion. The first level ontains Preprocessing Jobs with Multi-Criteria (PJMC) which will preprocess the jobs to elevate the user satisfaction and to itigate the jobs violation. In the second level, a Deadline Based Dynamic Priority Scheduler (DBDPS) is proposed which will ynamically prioritize the jobs for evading starvation. At the third level, Contest Mapping Jobs with Virtual Machine (CMJVM) is roposed that will map the job to suitable Virtual Machine (VM). In the last level, VM Scheduler is introduced in the two-tier VM rchitecture that will efficiently schedule the jobs and increase the resource utilization. These contributions will mitigate job iolations, avoid starvation, increase throughput and maximize resource utilization. Experimental results show that the performance f AMSS is better than other algorithms.

• ETRI Journal
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• v.26 no.4
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• pp.321-331
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• 2004

In this paper, we propose a new dynamic bandwidth allocation (DBA) algorithm for multimedia services over Ethernet PONs (passive optical networks). The proposed algorithm is composed of a low-level scheduler in the optical network unit (ONU) and a high-level scheduler in the optical line terminal (OLT). The hierarchical DBA algorithm can provide expansibility and efficient resource allocation in an Ethernet PON system in which the packet scheduler is separated from the queues. In the proposed DBA algorithm, the OLT allocates bandwidth to the ONUs in proportion to the weight associated with their class and queue length, while the ONU preferentially allocates its bandwidth to queues with a static priority order. The proposed algorithm provides an efficient resource utilization by reducing the unused remaining bandwidth caused by the variable length of the packets. We also define the service classes and present control message formats conforming to the multi-point control protocol (MPCP) over an Ethernet PON. In order to evaluate the performance, we designed an Ethernet PON system on the basis of IEEE 802.3ah "Ethernet in the first mile" (EFM) using OPNET and carried out simulations. The results are analyzed in terms of the channel utilization, queuing delay, and ratio of the unused remaining bandwidth.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Korea Society of Computer and Information
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• v.9 no.4 s.32
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• pp.173-178
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• 2004

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR. ABR) generated by a wide range of services ATM services the Quality-of-Service (QoS) management of traffice sources and bandwidth. Besides efficiency and throughput, the security services are achieved in the traffic sent in ATM network. In this paper, the scheduler evaluate and the packets sent in ATM security group. The scheduler transmits the safty packet, drop the unsafty packet and evaluate mark packet as the requirement of the delay. In this paper, we propose the scheduling algorithm of mark packet which evaluates the packet. The suggested model performance of the firewall switch is estimate simulation in terms of the delay by computer.

• Journal of the Korea Society for Simulation
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• v.23 no.4
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• pp.131-142
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• 2014

Phone camera lens module is assembled with a barrel, multiple lenses, multiple spacers and a shield. The major processes of manufacturing system are injection molding, coating and assembly processes, and each process has multiple machines. In this paper, we introduce a scheduler based on simulation model which can be used for frequent rescheduling problem caused by urgent orders, breaking down of molds and failures of machines. The scheduling algorithm uses heuristic Backward-Forward method, and the objective is to minimize the number of tardy orders.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.73-77
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• 2007

In this paper, we propose a VLSI architecture of an LMS filter based on a Cyclo-static scheduler for fast computation of LMS filteing algorithm which is widely used in adptive filtering area. This process is composed of two steps: scheduling and circuit synthesis. The scheduling step accepts a fully specified flow graph(FSFG) as an input, and generates an optimal Cyclo-static schedule in the sense of the sampling rate, the number of processors, and the input-output delay. Then the generated schedule is transformed so that the number of communication edges between the processors. The circuit synthesis part translates the modified schedule into a complete circuit diagram by performing resource allocations. The VLSI layout generation can be performed easily by an existing silicon compiler.