• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.2
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• pp.579-603
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• 2018

In this paper we propose a QoS-enhanced intelligent stochastic optimal fair real-time packet scheduler, QUEST, for 4G LTE traffic in routers. The objective of this research is to maximize the system QoS subject to the constraint that the processor utilization is kept nearly at 100 percent. The QUEST has following unique advantages. First, it solves the challenging problem of starvation for low priority process - buffered streaming video and TCP based; second, it solves the major bottleneck of the scheduler Earliest Deadline First's failure at heavy loads. Finally, QUEST offers the benefit of arbitrarily pre-programming the process utilization ratio.Three classes of multimedia 4G LTE QCI traffic, conversational voice, live streaming video, buffered streaming video and TCP based applications have been considered. We analyse two most important QoS metrics, packet loss rate (PLR) and mean waiting time. All claims are supported by discrete event and Monte Carlo simulations. The simulation results show that the QUEST scheduler outperforms current state-of-the-art benchmark schedulers. The proposed scheduler offers 37 percent improvement in PLR and 23 percent improvement in mean waiting time over the best competing current scheduler Accuracy-aware EDF.

• Convergence Security Journal
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• v.9 no.4
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• pp.13-19
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• 2009

In this paper, the integrated management of grid resources for conducting research on the global scheduler, the proposed plan is designed for. Research on the global scheduler and the grid system as a global scheduler for the system to understand the concept of a global scheduler configuration was necessary to check conditions. And other global scheduler, global positioning system and the differentiation of a ticket-based system was introduced to the concept. Finally, this paper proposed by the global scheduler for the system design, through prototyping to determine the actual effect can be used to determine whether is was.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.215-216
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• 2007

This paper presents a real-time scheduler for nuclear safety system. According to constraints and requirements of nuclear safety system, scheduler design analysis is done and algorithms are developed for implementation. Using DSP based hardware, a real-time scheduler is realized. Consequently, this paper shows the performance of periodical software through the monitoring program.

• The KIPS Transactions:PartC
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• v.12C no.5 s.101
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• pp.717-724
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• 2005

In this paper, we Propose an efficient scheduler well suited for the next-generation wireless networks that can support multimedia traffic having various requirements. The scheduler is designed to provide each of multimedia classes with differentiated services. In particular, the scheduler is intended to maximize throughput and minimize packet loss ratio. To apply the scheduler, we suppose that the wireless network is based on TDD/CDMA system The scheduler assigns a packet in a dedicated uplink-slot to the user within a frame to operate scheduling of packets transmitted by the users belonging to the specific class in an efficient manner. Such a manner also enables the scheduler to meet different QoS requirements. The paper also includes performance comparison with other schemes and analysis of the proposed scheduling algorithm by using simulation. We also analyze the proposed scheme by using simulation. The simulation compares the proposed scheduling algerian with previously proposed schemes in terms of the performance.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.13 no.2
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• pp.14-26
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• 2005

A tilt-rotor aircraft has various flight modes : helicopter, airplane, and conversion. Each of flight mode has unique and nonlinear flight characteristics. Therefore the gain schedules for whole flight envelope are required for effective flight performance. This paper proposes collective, flap, and nacelle angle scheduler for whole flight envelope of the Smart UAV(Unmanned Air Vehicle) based on CAMRAD(Comprehensive Analytical Model of Rotorcraft Aerodynamics and Dynamics) II analysis results. The scheduler designs are improved so that the pitch attitude angle of helicopter mode was minimized. The range of scheduler are reduced inside of engine performance limits. The conversion corridor and rotor governor are suggested also.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• Journal of Intelligence and Information Systems
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• v.1 no.1
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• pp.61-72
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• 1995

Dynamic and explicit ordering of strategies is a key process in modeling knowledge-level problem-solving behavior. This paper addressed the important problem of howl to make the scheduler more knowledge-intensive in a way that facilitates the acquisition, integration, and maintenance of the scheduler control knowledge. The solution a, pp.oach described in this paper involved formulating the scheduler task as a heuristic classification problem, and then implementing it as a classification expert system. By doing this, the wide spectrum of known methods of acquiring, refining, and maintaining the knowledge of a classification expert system are a, pp.icable to the scheduler control knowledge. One important innovation of this research is that of recursive heuristic classification : this paper demonstrates that it is possible to formulate and solve a key subcomponent of heuristic classification as heuristic classification problem. Another key innovation is the creation of a method of dynamic heuristic classification : the classification alternatives that are selected among are dynamically generated in real-time and then evidence is gathered for and aginst these alternatives. In contrast, the normal model of heuristic classification is that of structured selection between a set of preenumerated fixed alternatives.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• International Journal of Computer Science & Network Security
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• v.22 no.4
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• pp.394-400
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• 2022

The radio resources available in a wireless network system are limited. Therefor, job of managing resources is not easy task. Because the resources are shared among the UEs that are connected, the process of assigning resources must be carefully controlled. The packet scheduler in an LTE network is in charge of allocating resources to the user equipment (UE). Femtocells networks are being considered as a promising solution for poor channel performance for mulitple environments. The implementation of femtocells into a macrocell (traditional base station) would boost the capacities of the cellular network. To increase femtocells network capacity, a reliable Packet Scheduler mechanism should be implemented. The Packet Scheduler technique is introduced in this paper to maximize capacity of the network while maintaining fairness among UEs. The proposed solution operates in a manner consistent with this principle. An analysis of the proposed scheme's performance is conducted using a computer simulation. The results reveal that it outperforms the well-known PF scheduler in terms of cell throughput and average throughput of UEs.

• Journal of Information Processing Systems
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• v.17 no.6
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• pp.1157-1169
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• 2021

Modern graphics processor unit (GPU) architectures offer significant hardware resource enhancements for parallel computing. However, without software optimization, GPUs continuously exhibit hardware resource underutilization. In this paper, we indicate the need to alter different warp scheduler schemes during different kernel execution periods to improve resource utilization. Existing warp schedulers cannot be aware of the kernel progress to provide an effective scheduling policy. In addition, we identified the potential for improving resource utilization for multiple-warp-scheduler GPUs by sharing stalling warps with selected warp schedulers. To address the efficiency issue of the present GPU, we coordinated the kernel-aware warp scheduler and warp sharing mechanism (KAWS). The proposed warp scheduler acknowledges the execution progress of the running kernel to adapt to a more effective scheduling policy when the kernel progress attains a point of resource underutilization. Meanwhile, the warp-sharing mechanism distributes stalling warps to different warp schedulers wherein the execution pipeline unit is ready. Our design achieves performance that is on an average higher than that of the traditional warp scheduler by 7.97% and employs marginal additional hardware overhead.