• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.969-970
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• 2008

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2004.11a
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• pp.13-13
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• 2004

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.8
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• pp.1-7
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• 2019

When using conventional 3D image scanning methods, it is common for image scanning to be done manually, which is labor-intensive. Scanning a space made up of complicated equipment or scanning a narrow space that is difficult for the user to enter, is problematic, resulting in quality degradation due to the presence of shadow areas. This paper proposes a method to scan an image using a rover equipped with a scanner in areas where it is difficult for a person to enter. To control the scan path precisely, the 3D image remote scan automation method based on the rover move rule definition is described. Through the study, the user can automate the 3D scan plan in a desired manner by defining the rover scan path as the rule base.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.2
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• pp.186-194
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• 2004

Micro-stereolithography is a newly proposed technology as a means that can fabricate a 3D micro-structure of free form. It makes a 3D micro-structure by dividing the shape into many slices of relevant thickness along horizontal surfaces, hardening each layer of slice with a focused laser beam, and stacking them up to a desired shape. In this technology, differently from the conventional stereolithography, scale effect is dominant. To realize micro-stereolithography technology, we developed the micro-stereolithography apparatus which is composed of an Ar+ laser, x-y-z stages. controllers. optical devices and scan path generation software. Related processes were developed, too. Using the system, a number of micro-structures were successfully fabricated. Some of these samples are shown for prove this system. Laser scan path generation algorithm and software considering photopolymer solidification phenomena as well as given 3D model were developed. Sample fabrication of developed software shows relatively high dimensional accuracy compared to the uncompensated result.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.383-388
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• 2004

In this paper an alternative Active Matrix LCD technology is described with scalable, low cost processing. The Dual Select Diode AMLCD requires 60% lower capital investment in the array process than a-Si TFT arrays and results in 20% lower cost LCD modules. Development at several AMLCD manufacturers is in progress.

• The Journal of Korean Academy of Prosthodontics
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• v.61 no.3
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• pp.227-233
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• 2023

Tardive dyskinesia is an involuntary neurological movement disorder caused by long-term use of dopamine receptor-blocking drugs leading to dental implications like uncontrolled gnashing and grinding of teeth which in turn imperil the oral rehabilitation procedures as the excessive load increases the risk of prosthesis fracture. A 40-year male with a medical history of tardive dyskinesia visited the hospital to receive oral rehabilitation for missing maxillary anterior teeth. After the oral examination, tooth preparation was done on teeth 13, 15, and 23. After that silicon impression was made and the gypsum cast was digitalized using a desktop scanner and an interim prosthesis was fabricated by milling a resin block. During the try-in, the occlusal one-third of the interim prosthesis was trimmed, and an auto-polymerizing acrylic resin was applied on the occlusal surfaces and inserted in the patient's mouth. Then, the functionally generated path (FGP) of occluding surfaces of opposing arches was traced on the resin surface. When the resin was hardened, the modified interim prosthesis was removed and digitized using an intraoral scanner. The scan image was used in designing the occlusal morphology of definitive prosthesis by modifying the design of the interim prosthesis using the dual scan method. Lastly, a monolithic zirconia prosthesis was fabricated by milling a zirconia block. The definitive prosthesis was delivered reflecting the patient's occlusal scheme. This case report shows that the FGP technique with the dual scan method can help in fabricating fixed prosthesis with harmonious occlusion in a tardive dyskinesia patient.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.