• The Transactions of the Korea Information Processing Society
• /
• v.3 no.3
• /
• pp.572-580
• /
• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.1157-1159
• /
• 2003

The effect of the scan velocity modulation is studied. The effect of the velocity modulation on the picture image is judged from the intensity profile of the image. The intensity profile is obtained as time integral of moving Gaussian beam. To confirm the applicability of this integral formula, the measurement and simulation data is compared. And by calculating the intensity profile for different amounts of velocity modulation, the optimum modulation displacement that gives the best image quality is obtained. This optimum modulation displacement can be used in designing scan velocity modulation system.

• Journal of Electrical Engineering and Technology
• /
• v.4 no.4
• /
• pp.559-565
• /
• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.9
• /
• pp.85-91
• /
• 2013

This paper proposes the data reusable search scan methods for full search and fast search to implement low power Motion Estimation (ME). The proposed Optimized Sub-region Partitioning (OSP) method which divide search region into several sub-region can reduce the number of the required Reconfigurable Register Array (RRA) by half compared to the existing smart snake scan method for the same data reusability. In addition, the proposed Center Biased Search Scan method (CBSS) for various fast search algorithms can improve the data reusability. The performance comparisons show that the proposed search scan methods can reduce the average redundant data loading about 26.9% and 16.1% compared with the existing rater scan and snake scan methods, respectively. Due to the reduction of memory accesses, the proposed search scan methods are quite suitable for low power and high performance ME implementation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.873-877
• /
• 2005

Recent developments in Dual Select Diode (DSD) AMLCD technology are described. They include a novel array design and drive method with shared select lines, which leads to higher aperture ratio and a further reduction of module cost. A Color-On-Array DSD process and pixel layout compatible with In-Plane-Switching is also proposed.

• Fashion & Textile Research Journal
• /
• v.22 no.5
• /
• pp.650-659
• /
• 2020

The present study provides reference data required for the design of clothing for the elderly by analyzing the body surface area during fitness motion based on 3D scan data of Korean elderly women. This study was conducted with the procedures of (1) survey of motions and main muscles for fitness, (2) acquisition of 3D scan data, and (3) analysis of rate of change for body surface area during fitness motion. Acquisition of 3D body scan data was obtained from seven elderly females (age: 64-77). We selected 66 anatomical landmarks (40 upper body and 22 lower body) by referring to previous studies. Body surface was segmented by connecting the landmarks marked on the 3D scan data acquired. Analysis of body surface area was conducted in terms of the change rate of surface area in 9 postures of elbow 0°, 90° and 180° for flexion, shoulder 90°, 180° for flexion, shoulder 0°, 180° for abduction, hip 90° for flexion, and knee 90° for flexion compared to the those in the standing posture. The amount of changes in body surface area were 12%-62% in the upper body, 15%-77% in the arm, and 10%-51% in the lower body. A future study on the rate of change of body surface length is needed; in addition, a study on how to apply the results of body surface area and body surface length analysis to clothing pattern design is also necessary.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.1
• /
• pp.49-56
• /
• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.9 no.3
• /
• pp.116-122
• /
• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.130-133
• /
• 2003

Vertical Colour Selection (VCS) is an option for slim CRTs with increased sharpness and brightness. The direction of self-convergence of the DY is changed to vertical in order to obtain better spot uniformity, but the line scan direction remains horizontal. Hence, no video conversion is needed, contrary to transposed scan. In this paper we address two issues: First, there is a high risk of moire, since the scan lines and the phosphor stripes are parallel. We propose a feedback mechanism guiding the electron beams towards the middle of the mask slots. As positive side effects, the brightness is improved and the shadow mask can be made of a cheap type of steel. Secondly, VCS deflection coils have to satisfy different requirements than coils in ordinary CRTs. We discuss the design rules for self-convergent VCS coils and present simulation results.

• Journal of the Korean Society of Safety
• /
• v.20 no.3 s.71
• /
• pp.14-18
• /
• 2005

The ultrasonic handy scanner to be developed in this research is a nondestructive inspection equipment with various facility. The ultrasonic inspection is the technique area which apply range is increasing greatly with IT. The purpose of this research is development of a ultrasonic handy scan inspection device with the utility in a work spot. The ultrasonic handy scanner to be developed with portability in this research is able to carry out the spot inspection. It can contribute to the quality improvement, cost reduction and safety design.