• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2856-2858
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• 2000

This paper proposes a scan code method for obstacle avoidance of mobile robot. Obstacles detected in a circular window are converted to scan codes and then to the steering angle. The safe rotating radius is obtained by the scan code to avoid the collision between robot and obstacle and. the minimum distance for rotation is calculated. Effectiveness of the method is illustrated through simulations, and the results show that the proposed method can be efficiently implemented to an unknown environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.4
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• Proceedings of the Korean Nuclear Society Conference
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• 2001.05a
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• pp.89.1-89
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• 2001

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.5
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• pp.1412-1430
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• 2024

The soft cancellation list (SCANL) decoding algorithm for polar codes runs L soft cancellation (SCAN) decoders with different decoding factor graphs. Although it can achieve better decoding performance than SCAN algorithm, it has high latency. In this paper, a fast simplified SCANL (Fast-SSCANL) algorithm that runs L independent Fast-SSCAN decoders is proposed. In Fast-SSCANL decoder, special nodes in each factor graph is identified, and corresponding low-latency decoding approaches for each special node is propose first. Then, syndrome check aided Fast-SSCANL (SC-Fast-SSCANL) algorithm is further put forward. The ordinary nodes satisfied the syndrome check will execute hard decision directly without traversing the factor graph, thereby reducing the decoding latency further. Simulation results show that Fast-SSCANL and SC-Fast-SSCANL algorithms can achieve the same BER performance as the SCANL algorithm with lower latency. Fast-SSCANL algorithm can reduce latency by more than 83% compared with SCANL, and SC-Fast-SSCANL algorithm can reduce more than 85% latency compared with SCANL regardless of code length and code rate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1037-1040
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• 2002

In micro-stereolithography technology, fabrication conditions that include laser power, laser scan speed, laser scan pitch, and material property of photopolymer such as penetration depth and critical exposure are considered as major process variables. But the existing scan path generation methods based only on CAD model have not taken them into account, which has resulted in cross-section dimension of low accuracy. Thus, to enhance cross-section dimensional accuracy, the physical resin solidification n phenomena should be reflected in laser scan path generation and stage operating code. In this paper, multi-line experiments based on single line solidification model are performed. And the method for improving cross-section dimensional accuracy is presented, which is to apply the database based on experimental results to laser scan path generation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.115-121
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• 2004

GenJTAG implemented in this paper is an automatic web-based boundary scan circuit generator. GenJTAG supports all the public instructions for the boundary scan technique, and also private instructions for other DFT techniques to be applied. Users can easily edit the generated boundary scan circuit code because it is described in behavioral level with the Verilog-HDL. GenJTAG has another advantage that any one can generate the boundary scan circuit by simply accessing to the web site.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.256-259
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• 2003

This paper proposes OPTICAL MARKER fer registering process - one of the 3D measurement process : scan registering - merging - measurement. If the registering work is carried out manually, it can be accompanied with much time and many errors. Because the patterned marker make registering process automatic, many firms use it now. But the physical shape of existing markers is the source of the data loss caused by hiding surface, and the marker arrangement is the source of the time loss. The optical marker proposed in this paper has marker generator, organized a large number of binary coded control laser diode, separate from 3D scan object. So, it does not take much time for the marker disposition, and it is not the origin of the data loss, and the binary coded laser information make the auto-registering possible.