• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.113-122
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• 2020

Noise affects the accuracy of three-dimensional shape recovery. Its occurrence is unpredictable and depends on several mechanical, environmental, and other factors. When two-dimensional image sequences are obtained for shape from focus (SFF), mechanical vibration occurs in the translational stage, causing an error in the three-dimensional shape recovery. To address this issue, mechanical vibration is modeled using Newton's second law and the principle of the rack and pinion gear. Then, an optimal sampling step size considering the mechanical vibration is suggested through theoretical demonstration. Experiments conducted with real objects verify the effectiveness of the proposed sampling step size. In this paper, in a realistic environment with noise, the potential of obtaining more accurate three-dimensional reconstruction results of the objects is explored by acquiring the optimal sampling step size, which improves the sampling step size relative to those reported in a previous study performed under similar conditions.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.9
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• pp.710-715
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• 2016

Due to its simplicity and high reliability, the box-counting(BC) method is one of the most frequently used techniques to estimate the fractal dimensions of a binary image with a self-similarity property. The fractal calculation requires data sampling that determines the size of boxes to be sampled from the given image and directly affects the accuracy of the fractal dimension estimation. There are three non-overlapping regular grid methods: geometric-step method, arithmetic-step method and divisor-step method. These methods have some drawbacks when the image size M becomes large. This paper presents a BC algorithm for enhancing the accuracy of the fractal dimension estimation based on a new sampling method. Instead of using the geometric-step method, the new sampling method, called the coverage ratio-step method, selects the number of steps according to the coverage ratio. A set of experiments using well-known fractal images showed that the proposed method outperforms the existing BC method and the triangular BC method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Advances in Computational Design
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• v.1 no.3
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• pp.235-251
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• 2016

We have performed a design optimization of a stiffened panel with curvilinear stiffeners using an artificial neural network (ANN) residual kriging based surrogate modeling approach. The ANN residual kriging based surrogate modeling involves two steps. In the first step, we approximate the objective function using ANN. In the next step we use kriging to model the residue. We optimize the panel in an iterative way. Each iteration involves two steps-shape optimization and size optimization. For both shape and size optimization, we use ANN residual kriging based surrogate model. At each optimization step, we do an initial sampling and fit an ANN residual kriging model for the objective function. Then we keep updating this surrogate model using an adaptive sampling algorithm until the minimum value of the objective function converges. The comparison of the design obtained using our optimization scheme with that obtained using a traditional genetic algorithm (GA) based optimization scheme shows satisfactory agreement. However, with this surrogate model based approach we reach optimum design with less computation effort as compared to the GA based approach which does not use any surrogate model.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• Journal of the Korean Statistical Society
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• v.29 no.4
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• pp.435-441
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• 2000

Ko(1998, 1999) proposed certain flexible two-stage plans that could be served as one-step interim analysis in on-going clinical trials. The proposed Plans are optimal simultaneously in both a Bayes and a Neyman-Pearson sense. The Neyman-Pearson interpretation is that average expected sample size is being minimized, subject just to the two overall error rates $\alpha$ and $\beta$, respectively of first and second kind. The Bayes interpretation is that Bayes risk, involving both sampling cost and wrong decision losses, is being minimized. An example of this correspondence are given by using a binomial setting.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.867-870
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• 1999

In this paper, we designed a 8-bit flash ADC, which can be used in fully differential circuits. We adopted a 2-step flash architecture with digital correction. The designed ADC is expected to work at the sampling frequency of 30MHz. We carried out the layout with 0.65${\mu}{\textrm}{m}$ CMOS technology The core size is 1.587mm$\times$1.069mm.

• Bulletin of the Korean Chemical Society
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• v.34 no.6
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• pp.1703-1707
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• 2013

A fast and simple sampling and sample preparation device, (NTD) has been developed and applied to sample and analyze volatile components from ground coffee beans. Coffee fragrances and other volatile organic compounds (VOCs) were sampled by the NTD and then analyzed by gas chromatograph-mass spectrometry (GC/MS). Divinylbenzene (DVB) particles (80/100 mesh size) were the sorbent bed of the NTD. More than 150 volatile components were first identified based on the database of the mass library and then finally 30 fragrances including caffeine were further confirmed by comparing experimental retention indices (i.e. Kovat index) with literature retention indices. Total sampling time was 10 minutes and no extra solvent extraction and/or reconstitution step need. Straight n-alkanes (C6-C20) were used as retention index probes for the calculation of experimental retention indices. In addition, this report suggests that an empty needle can be an alternative platform for analyzing polymers by pyrolysis-GC/MS.

• Journal of Industrial Technology
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• v.21 no.B
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• pp.99-105
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• 2001

In this paper, the selective normalized constant modulus algorithm(SNCMA) is applied to a fractionally spaced equalizer. The fractionally spaced equalizer is insensitive to the sampling timing because it processes received signals with the sampling rate larger than the symbol rate. The SNCMA improves the convergence rate by using the large step size for the most outer covering symbol belonging to the trust-level. This blind equalizer exhibits a fast start-up convergence rate as well as a reduced steady-state residual error compared to the fractionally spaced blind equalizer and the T-spaced blind equalizer using conventional blind algorithms.

• International Journal of Reliability and Applications
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• v.17 no.1
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• pp.85-105
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• 2016

In this paper accelerated life testing is incorporated in quality control technique of acceptance sampling plan to induce early failures in high reliability products.Stress under accelerated condition can be applied in constant-stress, step-stress and progressive-stress or combination of such loadings. A ramp-stress results when stress is increased linearly (from zero) with time. In this paper optimum failure-censored ramp-stress accelerated life test sampling plan for log-logistic distribution has been formulated with cost considerations. The log-logistic distribution has been found appropriate for insulating materials. The optimal plans consist in finding optimum sample size, sample proportion allocated to each stress, and stress rate factor such that producer's and consumer's interests are safeguarded. Variance optimality criterion is used when expected cost per lot is not taken into consideration, and bilevel programming approach is used in cost optimization problems. The methods developed have been illustrated using some numerical examples, and sensitivity analyses carried out in the context of ramp-stress ALTSP based on variable SSP for proportion nonconforming.