• ETRI Journal
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• v.34 no.4
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• pp.553-563
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• 2012

Serial peripheral interface (SPI) has been identified as a bottleneck in many wireless sensing systems today. SPI is used almost universally as the physical connection between the microcontroller unit (MCU) and radios, storage devices, and many types of sensors. Virtually all wireless sensor nodes today perform up to twice as many bus transactions as necessary to transfer a given piece of data, as an MCU must serve as the bus master in all transactions. To eliminate this bottleneck, we propose the master-handoff protocol. After the MCU initiates reading from the source slave device and writing to the sink slave device, the MCU as a master becomes a slave, and either the source or the sink slave becomes the temporary master. Experiment results show that this master-handoff technique not only cuts the data transfer time in half, but, more importantly, also enables a superlinear energy reduction.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• Journal of IKEEE
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• v.27 no.4
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• pp.368-378
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• 2023

Automotive headlamp with LED matrix exploits low-cost low-speed serial buses such as I2C and SPI for digital LED control. When headlamp resolution increases, LED control data significantly increases to exceed capacity of control bus. This paper proposes HLCP (Headlamp LED Control Protocol), a novel LED maxtrix headlamp protocol. The proposed protocol exploits dedicated instructions to control many LEDs simultaneously, so it can control much more LEDs than conventional control buses although it is basically based on I2C bus. It is designed and verified in Verilog HDL. Simulation results show that HLCP can control LED matrix headlamp more efficiently than I2C and SPI.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.2
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• pp.161-170
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• 2017

The balise is a device for the railroad signal control systems, which is installed between both rail. The balise sends fixed or variable data, named telegram, to the train with wireless method. The telegram includes the position information, the movable distance under the signal status, the gradient, the speed, the temporary speed limit, etc. This research is on a design of the DBPL encoder for the balise. Normally the DBPL encoder for the balise is with the ASIC or FPGA technology. In this research, the DBPL encoder is designed with commercial low power operable micro-controller. The firmware(logic level encode) and the SPI Bus function block(physical level output) of the micro-controller are used for the DBPL encode. Under the european standard, the required working speed of the DBPL encoder is 564.48Kbps. The DBPL encoder of this research is tested under the speed of 564.48Kbps, and it worked properly.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1826-1829
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• 2005

Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)