• Analytical Science and Technology
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• v.15 no.1
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• pp.20-25
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• 2002

An accurate and simple analytical technique for $^{89}Sr$ and $^{90}Sr$, overcoming the demerits of the conventional method, has been developed with extraction chromatography and liquid scintillation counting. The Sr fraction was separated from hindrance elements with oxalate coprecipitation or cation exchange resin and purified with Sr-Spec column. With liquid scintillation counter, $^{89}Sr$ was measured by Cerenkov radiation method, and $^{90}Sr$ was measured by spectrum unfolding method. The developed radioactive strontium separation method was validated by application to the IAEA-reference material (IAEA-375, Soil) and radioactive waste samples.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.4
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• pp.945-951
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• 2008

In this paper, a new high performance data cache scheme that improves exploitation of both the spatial and temporal locality is proposed. The proposed data cache consists of a hardware prefetch unit and two sub-caches such as a direct-mapped (DM) cache with a large block size and a fully associative buffer with a small block size. Spatial locality is exploited by fetching and storing large blocks into a direct mapped cache, and is enhanced by prefetching a neighboring block when a DM cache hit occurs. Temporal locality is exploited by storing small blocks from the DM cache in the fully associative buffer according to their activity in the DM cache when they are replaced. Experimental results on Spec2000 programs show that the proposed scheme can reduce the average miss ratio by $12.53%\sim23.62%$ and the AMAT by $14.67%\sim18.60%$ compared to the previous schemes such as direct mapped cache, 4-way set associative cache and SMI(selective mode intelligent) cache[8].

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2686-2703
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• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

• Korean Journal of Agricultural Science
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• v.42 no.4
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• pp.389-396
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• 2015

This study was performed to investigate the opinions of various related-industries on ban of antibiotics growth promoters (AGPs) in commercial mixed feed. The answers on a total of 21 questions were summarized by response number and percentage. 93% of those surveyed were in agreement of a ban of dietary AGPs. The agreement reasons were the livestock safety (61.5%), the reduction of antibiotic use (23.1%), and decrease of antibiotic-resistant bacteria (11.5%). The negative effects expected by the ban of AGPs were poor growth performance (44.2%), elevated disease emergence (31.4%), increasing the feed cost (18.6%), and quality degradation of livestock (5.8%). As the efficient plans for decline of AGPs use, the feeding environment improvement was the highest with 43%, and farmer training and the consolidation inspection of residual substance on antibiotics in livestock product was 27.9% and 22.1%, respectively. 46.5% of respondent are considering the modification of feed spec and 39.5% of those surveyed have staged a modified feed spec. In conclusion, livestock related-industries approve a ban of AGPs, and they assert that the policy support, improvement of management and environment in the farm, providing technology from related-industries are multiply essential for a stable settlement of a ban policy of AGPs.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Journal of the Korea Convergence Society
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• v.11 no.7
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• pp.251-257
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• 2020

This study comparatively analyzed the differences in the talented human resources perceived by enterprises and job seekers in terms of recruitment trends of companies related to the 4th Industrial Revolution, focusing on 16 factors. The analysis data was collected from enterprises and job seekers related to the 4th Industrial Revolution, and the analysis method was applied to a convergence research methodology that mixes social network analysis and variance analysis using big data type. As a result, several things were verified. First, large enterprises emphasized communication, and small enterprises emphasized competency and confidence. Second, in the manufacturing industry, enterprises emphasized confidence and competence, and job seekers emphasized spec and passion. Third, in the service industry, enterprises emphasized personality and competence, and job seekers emphasized spec and global. Fourth, there was a big difference in talented human resources between enterprises and job seekers according to manufacturing and service industries. Based on these results, we discussed the opening of employment information for enterprises to reduce the recognition mismatch in the talented human resources.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.6
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• pp.667-673
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• 2004

The XML is emerging as standard language for data exchange on the Web. Therefore the demand of XML Schema(W3C XML Schema Spec.) that verifies XML document becomes increasing. However, XML Schema has a weak point for design because of its complication despite of various data and abundant expressiveness. This paper shows a simple way of design for XML Schema using a fundamental means for database design, the Entity-Relationship model. The conversion from the Entity-Relationship model to XML Schema can not be directly on account of discordance between the two models. So we present some algorithms to generate XML Schema from the Entity-Relationship model. The algorithms produce XML Schema codes using a hierarchical view representation. An important objective of this automatic generation is to preserve XML Schema's characteristics such as reusability, global and local ability, ability of expansion and various type changes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.2
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• pp.137-143
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• 2015

During the past 30 years, DRAM has been used for the reasons of economic efficiency of the production. Recently, PRAM has been emerged to overcome the shortcomings of DRAM. In this paper, we propose a technique that can reduce energy consumption by use of a narrow values to the write operation of PRAM. For this purpose, we describe the data compression method using a narrow value and the architecture of PRAM, We also experiment under the Simplescalar 3.0e simulator and SPEC CPU2000 benchmark environments. According to the experiments, the data hit rate of PRAM was increased by 39.4% to 67.7% and energy consumption was reduced by 9.2%. In order to use the proposed technique, it requires 3.12% of space overhead per word, and some additional hardware modules.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.123-128
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• 2012

In order to overcome the hardware complexity and performance limit problems, recently the multi-core architecture has been prevalent. For hardware simplicity, usually RISC processor is adopted as the unit core processor. However, if the performance of unit core processor is enhanced, the overall performance of the multi-core processor architecture can be further enhanced. In this paper, in-order superscalar processor is utilized as the core for the multi-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the number of superscalar cores between 2 and 16 and the window size of 4 to 16 extensively. As a result, the 16-core superscalar processor for the window size of 16 results in 8.4 times speed up over the single core superscalar processor. When compared with the same number of cores, the multi-core superscalar processor performance doubles that of the multi-core RISC processor.

• Journal of Internet Computing and Services
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• v.2 no.1
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• pp.23-30
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• 2001

ILP processors require an accurate branch prediction scheme to achieve higher performance. Two-Level branch predictor has been known to achieve high prediction accuracy. But, when a branch accesses a PHT entry that was, previously updated by other branch, Two-level predictor may cause interferences. Negative interferences among all interferences have a negative effect on performance, since they can cause branch mispredictions. Agree predictor achieve high prediction accuracy by converting negative interferences to positive interferences by adding bias bits to BTB, but negative interferences may occur when bias bit is set incorrectly. This paper presents a new dynamic branch predictor which reduces negative interferences. In the proposed predictor, we attach hit bits to entries in BTB to change bias bit dynamically during the execution time, h a result the proposed scheme improve the accuracy of prediction by reducing negative Interferences effectively, To illustrate the effect of the proposed scheme, we evaluate the performance of this scheme using SPEC92int benchmarks, The results show that the proposed scheme can outperform traditional branch predictors.