Browse > Article
http://dx.doi.org/10.7236/JIIBC.2015.15.2.137

Reducing Method of Energy Consumption of Phase Change Memory using Narrow-Value Data  

Kim, Young-Ung (Dept. of Computer Eng., Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.15, no.2, 2015 , pp. 137-143 More about this Journal
Abstract
During the past 30 years, DRAM has been used for the reasons of economic efficiency of the production. Recently, PRAM has been emerged to overcome the shortcomings of DRAM. In this paper, we propose a technique that can reduce energy consumption by use of a narrow values to the write operation of PRAM. For this purpose, we describe the data compression method using a narrow value and the architecture of PRAM, We also experiment under the Simplescalar 3.0e simulator and SPEC CPU2000 benchmark environments. According to the experiments, the data hit rate of PRAM was increased by 39.4% to 67.7% and energy consumption was reduced by 9.2%. In order to use the proposed technique, it requires 3.12% of space overhead per word, and some additional hardware modules.
Keywords
Phase Change Memory(PRAM); Narrow value; Data hit rate; Energy consumption;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Z. Shao, "Utilizing PCM for Energy Optimization in Embedded Systems," VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, 398-403 pages, 19-21 Aug. 2012.
2 A. Mirhoseini, M. Potkonjak, and F. Koushanfar, "Coding-based energy minimization for phase change memory," DAC '12 Proceedings of the 49th Annual Design Automation Conference, Pages 68-76 , 2012.
3 S. Cho and H. Lee, "Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance," 42nd Annual IEEE/ACM International Symposium, pages, 12-16 Dec. 2009.
4 T. Liu, Y. Zhao. C. Xue, and M. Li, "Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory," Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages, 5-9 Jun. 2011.
5 O. Ergin et al, "Exploiting narrow values for soft error tolerance," IEEE Computer Architecture Letters, 2006.
6 J Kim, S Kim, Y Lee, SimTag: exploiting tag bits similarity to improve the reliability of the data caches, Proceedings of the Conference on Design, and Test in Europe, 08-12, Mar. 2010.
7 D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. Computer Architecture News, pages 13-25, Jun. 1997.
8 The Standard Performance Evaluation Corporation. Spec CPU2000 suite. http://www.specbench.org/osg/cpu2000/.
9 ARM Cortex A8 processor, "http://www.arm.com/products/processors/cortex-a/cortex-a8.php"
10 Y. Kim, "Improving Reliability of the Last Level Cache with Low Energy and Low Area Overhead"The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), pages, 35-41, Apr. 2012.