• Journal of Power Electronics
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• v.16 no.4
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.251-254
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• 2008

유비쿼터스 네트워크의 실현을 위한 4세대 통신방식의 유력한 후보로 부상하는 OFDM (Orthogonal Frequency Division Multiplexing) 통신방식이 육상에 주목받고 있으며, 고속 데이터 전송을 위한 무선랜의 표준기술로 확정되어 있다. 해상 통신의 경우에서도 OFDM 통신방식은 단파대역을 이용한 데이터 전송방식으로 제안되고 있으며, ITU (International Telecommunication Union)는 해상통신에서 32-point FFT를 사용하도록 권고하고 있다. 해상 통신에서는 해양사고 및 조난 시에도 통신이 이루어져야 하는 한계상황을 고려하면, OFDM 통신방식의 중요 디바이스인 FFT는 저전력으로 동작되어야 한다. 따라서 본 논문에서는 OFDM 방식의 중요 디바이스인 32-point FFT를 저전력으로 동작시키기 위해 radix-2와 radix-4를 이용하여 저전력 32-point FFT 알고리즘을 제안한다. 최적화된 설계로 32-point FFT를 저전력 동작이 가능하도록 설계하였으며, 제안한 알고리즘은 VHDL로 구현하고 FPGA Spartan3 board에 장착하여 Matlab의 이론값과 비교, 검증하였다. 제안된 32-point FFT는 해상통신에서의 OFDM 적용을 위한 선도기술로 유용할 것이다.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.292-299
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• 2021

A form of data mining software, based on manufacturing-based IIoT environment with the development of IT technologies are increasingly growing. However, it is difficult to evaluate the software quality in the same form as general software due to the characteristics of the software of a manufacturing company that has a large amount of data that needs to be carried out with big data and data mining. In addition, in a manufacturing-based environment where heterogeneous equipment and software are mixed, it is difficult to perform quality judgment on software used by applying existing quality characteristics. Therefore, in this paper, the characteristics of the manufacturing base are investigated, and a software quality evaluation model suitable for it is developed and evaluated.

• Journal of Electrical Engineering and Technology
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• v.12 no.1
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• pp.78-90
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• 2017

This paper presents the design of closed loop controllers operating a single-phase AC-DC three-level converter for improving power quality at AC mains. Closed loop inhibits outer voltage controller and inner current controller. Simulations of three level converter with three different voltage and current controller combinations such as PI-Hysteresis, Fuzzy-Hysteresis and Fuzzy tuned PI-Hysteresis are carried out in MATLAB/Simulink. Performance parameters such as input power factor and source current total harmonic distortion (THD) are considered for comparison of the three controller combinations. The fuzzy-tuned PI voltage controller with hysteresis current controller combination provides a better result, with a source-current THD of 0.93% and unity power factor without any source side filter for the three level converter. For load variations of 25% to 100%, a THD of less than 5% is obtained with a maximum value of only 1.67%. Finally, the fuzzy-tuned PI voltage with hysteresis controller combination is implemented in a Xilinx Spartan-6 XC6SLX25 FPGA board for experimental validation of power quality enhancement. A prototype 100 W, 0-24-48 V as output converter is considered for the testing of controller performance. A source-current THD of 1.351% is obtained in the experimental study with a power factor near unity. For load variations of 25% to 100%, the THD is found to be less than 5%, with a maximum value of only 2.698% in the experimental setup which matches with the simulation results.

• Journal of the Korean Society of Food Science and Nutrition
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• v.43 no.3
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• pp.419-424
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• 2014

Metabolite profiling of blueberry (cultivar "Spartan") was performed by extraction using different solvents, methanol and ethyl acetate, through metabolomic analysis using LC-MS/MS. Unsupervised classification method (PCA) and supervised prediction model (OPLS-DA) provided good categorization of metabolites according to the extraction solvents. Metabolites of the anthocyanin family, including delphinidin hexoside, delphinidin, 5-O-feruloylquinic acid, malvidin hexoside, malvidin-3-arabinoside, petunidin-3-arabinoside, and petunidin hexoside, were mainly detected in methanol fractions, whereas those of the flavonoid family, including chlorogenic acid, chlorogenic acid dimer, 6,8-di-C-arabinopyranosyl-luteolin, and luteolin were successfully prepared in the ethyl acetate fraction. Thus, metabolomic analysis of blueberry extracts allows for the simple profiling of whole and distinctive metabolites for future applications.

• Convergence Security Journal
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• v.7 no.2
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• pp.17-25
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• 2007

In this paper, an algorithm that provisions proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features an adaptive scheme that adjusts the target delay every time slot to compensate the deviation from the target delay which is caused by the prediction error on the traffic to be arrived in the next time slot. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential rate traffic. It is demonstrated through simulations that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA and the performance is verified under the test board based on the XPC860P CPU.