• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.119-126
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• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.375-378
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• 2007

This paper describes indoor location estimation intelligent robot. It is loaded indoor location estimation function using RSSI based indoor location estimation system and wireless sensor networks. Spartan III(Xilinx, U.S.A.) is used as a main control device in the mobile robot and the current direction data is collected in the indoor location estimation system. The data is transferred to the wireless sensor network node attached to the mobile robot through Zigbee/IEEE 802.15.4, a wireless communication. After receiving it, with the data of magnetic compass the node is aware of and senses the direction the robot head for and the robot moves to its destination. Indoor location estimation intelligent robot is can be moved efficiently and actively without obstacle on flat ground to the appointment position by user.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.109-114
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• 2010

In this paper, the implementation of a human signal sensing module that has capabilities to check and restore the weak signals from the human body is presented. A module presented in this paper consists of processing and sensing elements related to human pulse and body temperature and a controller implemented with SoC design method. PPG data is detected by a noise filtering process toward the amplified signal which is from the operating frequency between 0.1Hz - 10Hz. A digital temperature sensor is used to check the body temperature. A sensor outputs the corresponding value of the electric voltage according to the body temperature. Moreover, this paper discusses the implementation of an enhanced microprocessor which is synthesized with VHDL as a part of the SoC development and used to control the entire module. The SoC processor is implemented on a Xilinx Spartan 3 XC3S1000 device and has the achieved operating frequency of 10MHz. The implemented SoC processor core is successfully tested with macro memories in FPGA and the experimental results are hereby shown.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.449-452
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• 2007

An intelligent robot with RSSI based indoor location estimation function was designed and implemented. A wireless sensor node was attached to the robot to received the location data from the indoor location estimation function. Spartan III was used as the main control device in the mobile robot. The current location data collected from the indoor location estimation system was transferred to the mobile robot and server through Zigbee/IEEE 802.15.4 wireless communication of the sensor node. Once the location data is received, the sensor node senses the direction of the robot head and directs the robot to move to its destination. Indoor location estimation intelligent robot is able to move efficiently and actively to the user appointed location by implementing the proposed obstacles avoidance algorithm. This system is able to monitor real-time environmental data and location of the robot using PC program. Indoor location estimation intelligent robot also can be controlled by executing the instructions sent from the PC program.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.1-6
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• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.145-151
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• 2009

Orthogonal Frequency Division Multiplexing (OFDM) has been focused on as 4th generation communication method for realization of Ubiquitous Network in land mobile communications services, and has been a standard technology of Wireless Local Area Network (WLAN) for a High Date Rate communication. And in maritime data communication using high frequency (HF) band, 32-point FFT OFDM system is recommended by International Telecommunication Union (ITU). Maritime communication should be kept on connecting when maritime accident or the maritime disaster happen. Therefore, main device FFT should be operated with low power consumption. In this paper we propose a low power 32-point FFT algorithm using radix-2 and radix-4 for low power operation. The proposed algorithm was designed using VHSIC hardware description language (VHDL), and it was confirmed that the output value of Spartan-3 field-programmable gate array (FPGA) board corresponded to the output value calculated using Matlab. The proposed 32-point FFT algorithm will be useful as a leading technology in a HF maritime data communication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1195-1200
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• 2007

This paper describes indoor location estimation intelligent robot. Indoor location estimation function using RSSI based indoor location estimation system and wireless sensor networks were implemented in the robot. Spartan III(Xilinx, U.S.A.) was used as a main control device in the mobile robot and the current direction data was collected in the indoor location estimation system. The data was transferred to the wireless sensor network node attached to the mobile robot through Zigbee/IEEE 802.15.4, a wireless communication. After receiving it, with the data of magnetic compass the node is aware of and senses the direction the robot head for and the robot moves to its destination. Indoor location estimation intelligent robot is can be moved efficiently and actively without obstacle on flat ground to the appointment position by user.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.1-6
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• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.