• Atmosphere
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• v.33 no.3
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• pp.319-330
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• 2023

As the need for PM type observation increases, Surface Particulate Matter Network (SPARTAN), PM samplers analyzes aerosol samples for PM mass concentration and chemical composition, were recently installed at two sites: Yonsei University at Seoul and Ulsan Institute of Science and Technology (UNIST) at Ulsan. These SPARTAN filter samplers and nephelometers provide the PM_2.5 mass concentration and chemical speciation data with aerosol type information. We introduced the overall information and installation of SPARTAN at the field site in this study. After installation and observation, both Seoul and Ulsan sites showed a similar time series pattern with the daily PM_2.5 mass concentration of SPARTAN and the data of Airkorea. In particular, in the case of high concentrations of fine particles, daily average value of PM_2.5 was relatively well-matched. During the Yonsei University observation period, high concentrations were displayed in the order of sulfate, black carbon (BC), ammonium, and calcium ions on most measurement days. The case in which the concentration of nitrate ions showed significant value was confirmed as the period during which the fine dust alert was issued. From the data analysis, SPARTAN data can be analyzed in conjunction with the existing urban monitoring network, and it is expected to have a synergetic effect in the research field. Additionally, the possibility of being analyzed with optical data such as AERONET is presented. In addition, the method of installing and operating SPARTAN has been described in detail, which is expected to help set the stage for the observation system in the future.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.768-770
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• 2010

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embeded systems.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.428-430
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• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.834-837
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• 2015

In this paper, we designed the FPGA hardware-based real-time ECG simulator, which generates an analog ECG signal within the range of 0 to 5 volts and described function. The ECG signal generated by the simulator can be applied to laboratory tests, the medical device, and the calibration study in various ways. ECG signals generated by simulator are obtained with conventional 24bit quantization to generate the signal data, and they are sampled and quantized to 1kHz of the 8-bit resolution when used as actual data. The proposed simulator is implemented using xilix Spartan-3 and data are transmitted through an RS-232 between the PC and the FPGA simulator. The transmitted data are stored in the memory and the stored data are printed out with the analog ECG signal through DAC (0808). It can also control the heart rate (HR) via the two buttons level UP-DOWN. We used existing ECG input rating for the evaluation of the designed system and evaluated differential circuit for obtaining QRS waveform and the output signal. We finally could obtained proper the result.

• Journal of IKEEE
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• v.24 no.1
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• pp.52-58
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• 2020

This paper describes a hardware implementation of a true random number generator (TRNG) for information security applications. A new approach for TRNG design was proposed by adopting random transition rules in cellular automata and applying different transition rules at every time step. The TRNG circuit was implemented on Spartan-6 FPGA device, and its hardware operation generating random data with 100 MHz clock frequency was verified. For the random data of 2×10⁷ bits extracted from the TRNG circuit implemented in FPGA device, the randomness characteristics of the generated random data was evaluated by the NIST SP 800-22 test suite, and all of the fifteen test items were found to meet the criteria. The TRNG in this paper was implemented with 139 slices of Spartan-6 FPGA device, and it offers 600 Mbps of the true random number generation with 100 MHz clock frequency.

• Aerospace Industry
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• s.97
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• pp.62-63
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• 2007

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.4
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• pp.335-342
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• 2021

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.452-459
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• 2020

The electric actuator receives the user's command input signal (open/closed/stop), checks the status of various sensors (valve position, rotational force, motor status, etc.)in the actuator, and controls the motor forward/reverse to open and close the valve. It is a device that outputs the current state of an actuator (valve) and is used in various fields such as dams, power plants, water and sewage facilities, and oil pipeline facilities. If an electric actuator is installed in a power plant and a problem occurs during operation, it can cause a large economic loss, so system reliability is vert important. In this study, in order to increase the safety of the electric actuator, the development of an electric actuator control device capable of setting the ON/OFF time in hardware was conducted to solve the reliability problem that may occur in software. In addition, the electric actuator control device development environment was developed using Xilinx's Spartan7 FPGA and Altium tool.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.