• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.126-129
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point, the passivation potential (PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2000년도 춘계학술대회 논문집(Proceeding of the KOSME 2000 Spring Annual Meeting)
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• pp.105-109
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• 2000

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor the size of the pressure sensor diaphragm have become smaller year by year and a microaccelerometer with a size less than 200-300${\mu}m$ has been realized. In this paper we study some of the micromachining processes of SOI(silicon on insulator)for the microaccelerometer and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in structural engineering discipline for design of SOI wafers. Successful thermal behaviors analysis and design of the SOI wafers based on the tunneling current concept using SOI wafer depend on the knowledge abut normal mechanical properties of the SCS(single crystal silicon)layer and their control through manufacturing process

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.695-698
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• 2008

We investigated the characteristics of Strained-Si-on-Insulator (sSOI) MOSFETs with 0.7% tensile strain. The sSOI MOSFETs have superior subthreshold swing under 70 mV/dec and output current. Especially, the electron and hole were increased in sSOI MOSFET. The electron and hole mobility in sSOI MOSFET were 286$cm^2/Vs$ and 151$cm^2/Vs$, respectively. The carrier mobility enhancement is due to the subband splitting by 0.7% tensile strain.

• 전자공학회논문지 IE
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• 제45권2호
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• pp.1-5
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• 2008

본 연구에서는 SOI MOSFET를 hot carrier 현상에 의한 RF 성능 저하를 측정 분석하였다. $V_{GS}=0.8V$, f=2.5GHz에서 설계되어 진 LNA의 이득은 16.51dB이고 잡음지수는 1.195dB였다. SOI에서 스트레스 후에는 LNA의 이득과 잡음지수가 스트레스전보다 각각 15.3dB, 1.44dB로 변화하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.707-710
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• 2003

10nm 이하의 두께를 갖는 얇은 SOI 층 위에서 우수한 동작 특성을 보이는 Fully-Depleted SOI nMOSFET 을 제작하였다. 게이트의 길이가 큰 경우에는 SOI 층이 얇지 않아도 좋은 특성을 보이지만, 게이트 길이가 100nm 이하에서는 Short Channel Effect 에 의한 특성 열화 때문에 SOI thin body 의 두께가 게이트 길이에 따라 같이 얇아져야 한다. [1] 100nm 게이트 길이 SOI-NMOSFET에서 10nm 이하 body 두께에 따라 Vth는 조금 상승했고, Subthreshold slope은 조금 개선되는 특성을 보였다. 또한, 45nm 게이트 길이와 3nm 로 추정되는 body 두께를 갖는 nMOSFET 에서 우수한 I-V 동작 특성을 얻었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.86-89
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• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.