• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.75-80
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• 2004

By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.873-876
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• 2001

본 논문에서는 고속 데이터 전송을 위한 OFDM (Orthogonal Frequency Division Multiplex) 시스템용 고속 FFT 프로세서를 제안한다. 적은 하드웨어 크기를 만족하기 위해 단일 메모리 구조를 채택하였으며 고속 연산을 위해 Radix-4 알고리즘과 메모리 뱅크 구조를 사용하였다. 또한, 버터 플라이 출력이 입력 데이터의 위치에 저장되는 In-place 메모리 구조를 갖는다. 설계한 프로세서는 VHDL로 모델링하여 삼성 0.5㎛ SOG 공정으로 합성하였으며 메모리를 제외한 전체 게이트 수가 98,326개를 보였다. 동작속도는 42MHz로 256-포인트 연산이 6㎲에 처리 가능한 구조이다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1275-1278
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• 2006

A display panel image data manipulator for SOP or SOG is presented. It is capable of all the shift operations for MPEG decoders, graphic processors and controllers as well as data pack, merging, bit split and reformation operations to improve speed and memory utilization. To alleviate poly-Si low yield, redundancy based fault recovery scheme is introduced utilizing regular structure.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1635-1639
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• 2006

LTPS has potential capability to realize various kinds of circuit integrations on panel glass because of its relatively higher field effect mobility of around 100cm2/Vs. Recent progress of LTPS technologies and advanced technologies, which are generally called "System on Glass (SOG)," will be discussed. The technology includes circuit integration, photo-sensor integration for input functions, and display quality and performance improvement.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1447-1450
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• 2006

The high speed and sensitivity array test system has been developed and utilized for massproduction of advanced LTPS displays including SOG and OLED. It realizes fast enough TACT enabling 100% inspection with better than 1fF sensitivity. The result of actual measurement shows its superior TACT and sensitivity, and also shows MURA detection of OLED panel.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04b
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• pp.610-612
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• 2002

본 논문은 오프라인 필기체 숫자 인식을 위하여 SOG* 세선화와 방향 코드 생성만으로 전처리를 단순화하여 효율을 높이는 새로운 방법을 제안한다. 본 실험의 객관적 검증을 위해 Concordia 대학교 등의 여러기관의 필기체 숫자 데이터베이스에 대하여 실험한 결과 98.85% 이상의 인식률을 나타내어 단순한 전처리로 높은 인식률을 얻음으로써 효율성이 높음을 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.12
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• pp.513-519
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• 2002

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing(OFDM) systems. The Proposed architecture uses a single-memory architecture and uses a radix-4 algorithm for high speed. The proposed memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. Therefore, the memory size can be reduced. The SQNR of about 80dB is achieved with 20-bit input and 20-bit twiddle factors. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0.5㎛ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding memory. It has smaller hardware than existing pipeline FFT processors for more than 1024-point FFTs. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6us. It satisfies tile required processing speed of 8.4㎲ in the HomePlug standard.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.171-176
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• 2000

The physical and electrical characteristics of MgO and Pt thin-films on it, deposited by reactive sputtering and rf magnetron sputtering, respectively, were analyzed with annealing temperature and time by four-point probe, SEM and XRD. Under annealing conditions of $1000^{\circ}C$ and 2 hr, MgO thin-film had the properties of improving Pt adhesion to $SiO_2$ and insulation without chemical reaction to Pt thin-film, and the sheet resistivity and the resistivity of Pt thin-film deposited on it were $0.1288\;{\Omega}/{\square}$ and $12.88\;{\mu}{\Omega}{\cdot}cm$, respectively. We made Pt resistance pattern on $SiO_2$/Si substrate by lift-off method and fabricated thin-film type Pt-RTD(resistance thermometer device) for micro thermal sensors by Pt-wire, Pt-paste and SOG(spin-on-glass). In the temperature range of $25{\sim}400^{\circ}C$, the TCR value of fabricated Pt-RTD with thickness of $1.0{\mu}m$ was $3927\;ppm/^{\circ}C$ close to the Pt bulk value. Resistance values were varied linearly within the range of measurement temperature.

• Resources Recycling
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• v.20 no.3
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• pp.55-61
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• 2011

In order to develop economical production process from metallurgical grade silicon(MG-Si) to solar grade(SOG-Si), removal of boron by slag treatment was investigated at 1823 K using CaO-$SiO_2$ based slags. In the present study boron removal ratio in CaO-$SiO_2$ stags and $CaCO_3-SiO_2$ slags were increased to 63% and 73% respectively with slag basicity (%CaO/$%SiO_2$). However, bubbling time with Ar gas of slag and metal was not affected on removal ratio of boron. The addition of $Na_2CO_3$ to CaO-$SiO_2$ slags did not improve the removal ratio of boron from molten silicon. Boron contend was decreased from 20.6 ppm to 1.03 ppm by three times treatment using $CaCO_3-SiO_2$ slag (basicity=1.2).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.