• 한국진공학회지
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• 제12권3호
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• pp.168-173
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• 2003

유리 기판 위에 증착된 비정질 실리콘 박막의 고상 결정화에 대한 새로운 방법을 제시하였다. 비정질 실리콘 박막의 하부에 패턴 된 다양한 크기의 $TiSi_2$ 박막을 전기저항 가열 방식으로 가열함으로서 비정질 실리콘이 고상 결정화 되도록 하였다. 박막히터를 이용한 열처리는 매우 빠른 열처리 공정으로써, 일반적인 로에 의한 열처리에 비해 매우 낮은 thermal budget을 가지므로, 유리기판 위에서도 고온 열처리가 가능하다는 장점을 가진다. 본 연구에서는 500 $\AA$의 비정질 실리콘 박막을 약 $850^{\circ}C$ 이상의 높은 온도에서 수 초 내에 결정화 할 수 있음을 보였으며, 열처리 조건의 변화에 따른 영향과 지역선택성의 장점을 보였다.

• 한국해양공학회지
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• 제16권6호
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• pp.60-64
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• 2002

This paper describes the machining characteristics of the MoSi$_2$--based composites through the process of electric discharge drilling with various tubular electrodes. In addition to hardness characteristics, microstructures of Nb/MoSi$_2$laminate composites were evaluated from the variation of fabricating conditions, such as preparation temperature, applied pressure, and pressure holding time. MoSi$_2$-based composites have been developed in new materials for jet engines of supersonic-speed airplanes and gas turbines for high-temperature generators. These high performance engines may require new hard materials with high strength and high temperature-resistance. Also, with the exception of grinding, traditional machining methods are not applicable to these new materials. Electric discharge machining (EDM) is a thermal process that utilizes a spark discharge to melt a conductive material. The tool electrode is almost -unloaded, because there is n direct contact between the tool electrode and the work piece. By combining a non-conducting ceramic with more conducting ceramic, it was possible to raise the electrical conductivity. From experimental results, it was found that the lamination from Nb sheet and MoSi$_2$ powder was an excellent strategy to improve hardness characteristics of monolithic MoSi$_2$. However, interfacial reaction products, like (Nb, Mo)SiO$_2$and Nb$_2$Si$_3$formed at the interface of Nb/MoSi$_2$, and increased with fabricating temperature. MoSi$_2$composites, with which a hole drilling was not possible through the conventional machining process, enhanced the capacity of ED-drilling by adding MbSi$_2$, relative to that of SiC or ZrO$_2$reinforcements.

• 한국재료학회지
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• 제12권1호
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• pp.48-53
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• 2002

$Al_2O_3-SiC$ and $Al_2O_3-SiC$-TiC composite powders were prepared by SHS process using $SiO_2,\;TiO_2$, Al and C as raw materials. Aluminum powder was used as reducing agent of $SiO_2,\;TiO_2$ and activated charcoal was used as carbon source. In the preparations of $Al_2O_3-SiC$, the effect of the molar ratio in raw materials, compaction pressure, preheating temperature and atmosphere were investigated. The most important variable affecting the synthesis of $Al_2O_3-SiC$ was the molar ratio of carbon. Unreactants remained in the product among all conditions without compaction. The optimum condition in this reaction was $SiO_2$: Al: C=3: 5: 5.5, 80MPa compaction pressure under Preheating of $400^{\circ}C$ with Ar atmosphere. However there remains cabon in the optimum condition. The effect of $TiO_2$ as additive was investigated in the preparations of $Al_2O_3-SiC$. As a result of $TiO_2$ addition, $Al_2O_3-SiC$-TiC composite powder was prepared. The $Al_2O_3$ powder showed an angular type with 8 to $15{\mu}m$, and the particle size of SiC powder were 5~$10{\mu}m$ and TiC powder were 2 to $5{\mu}m$.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1998년도 PROCEEDINGS OF THE 14TH KACG TECHNICAL MEETING AND THE 5TH KOREA-JAPAN EMGS (ELECTRONIC MATERIALS GROWTH SYMPOSIUM)
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• pp.173-176
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• 1998

Epitaxial Si layers were deposited on n- or p-type Si(100) substrates by hot-wall chemical vapor deposition (CVD) technique using the {{{{ {SiH }_{ 2} {Cl }_{2 } - {H }_{ 2} }}}}chemistry. Thermodynamic calculations if the Si-H-Cl system were carried out to predict the window of actual Si deposition procedd and to investigate the effects of process variables(i.e., the deposition temperature, the reactor pressure, and the source gas molar ratios) on the growth of epitaxial layers. The calculated optimum process conditions were applied to the actual growth runs, and the results were in good agreement with the calculation. The expermentally determined optimum process conditions were found to be the deposition temperature between 900 and 9$25^{\circ}C$, the reactor pressure between 2 and 5 Torr, and source gad molar ration({{{{ {H }_{2 }/ {SiH }_{ 2} {Cl }_{2 } }}}}) between 30 and 70, achieving high-quality epitaxial layers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.117-122
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• 2001

In this paper, we report on photoelectrochemical etching process of 6H-SiC semiconductor wafer. The etching was performed in two-step process; anodization of SiC surface to form a deep porous layer and thermal oxidation followed by an HF dip. Etch rate of about 615${\AA}$/min was obtained during the anodization using a dilute HF(1.4wt% in H$_2$O) electrolyte with the etching potential of 3.0V. The etching rate was increased with the bias voltage. It was also found out that the adition of appropriate portion of H$_2$O$_2$ into the HF solution improves the etching rate. The etching process resulted in a higherly anisotropic etching characteristics and showed to have a potential for the fabrication of SiC devices with a novel design.

• Journal of information and communication convergence engineering
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• 제5권3호
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• pp.215-218
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• 2007

In this paper, amorphous semiconductor and insulator thin film are etched using reactive ion etcher. At that time, we experiment in various RIE conditions (chamber pressure, gas flow rate, rf power, temperature) that have effects on quality of thin film. The using gases are $CF_4,\;CF_4+O_2,\;CCl_2F_2,\;CHF_3$ gases. The etching of a-Si:H thin film use $CF_4,\;CF_4+O_2$ gases and the etching of $a-SiO_2,\;a-SiN_x$ thin film use $CCl_2F_2,\;CHF_3$ gases. The $CCl_2F_2$ gas is particularly excellent because the selectivity of between a-Si:H thin film and $a-SiN_x$ thin film is 6:1. We made precise condition on dry etching with uniformity of 5%. If this dry etching condition is used, that process can acquire high yield and can cut down process cost.

• Current Applied Physics
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• 제18권11호
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• pp.1436-1440
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• 2018

SiN and SiCN film production using plasma-enhanced atomic layer deposition (PE-ALD) is investigated in this study. A developed high-power and high-density multiple inductively coupled plasma (multi-ICP) source is used for a low temperature PE-ALD process. High plasma density and good uniformity are obtained by high power $N_2$ plasma discharge. Silicon nitride films are deposited on a 300-mm wafer using the PE-ALD method at low temperature. To analyze the quality of the SiN and SiCN films, the wet etch rate, refractive index, and growth rate of the thin films are measured. Experiments are performed by changing the applied power and the process temperature ($300-500^{\circ}C$).

• 한국염색가공학회지
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• 제33권4호
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• pp.309-316
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• 2021

Due to the rigid nature of the silicon carbide fiber(SiC), fiber damage occurs from the friction during the carding process. This damage not only lowers the spun yarn yield, but also lowers the heat resistance of the spun yarn, so that ultra-high heat resistant yarn cannot be manufactured. Therefore, in the carding process where the most friction between fiber and machine(wire, etc.) occurs, some factors were modified and tested, and as a result of measuring the change in physical properties, fiber damage decreased due to the wire angle or wire density, resulting in improved yield. The test method used to measure the yield of SiC fiber was the carbonization method, and the content of SiC fibers was calculated using the remaining amount after carbonization. Carbonization test was performed at air condition, 700℃, and for 2 hours. Analysis by SEM-EDX showed that the carbide was consistent with the composition of the SiC fiber.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.